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8298189: Regression in SPECjvm2008-MonteCarlo for pre-Cascade Lake Intel processors

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Co-authored-by: Quan Anh Mai <qamai@openjdk.org>
Reviewed-by: shade, thartmann, kvn
This commit is contained in:
Roberto Castañeda Lozano
2023-04-26 08:25:11 +00:00
parent 44d9f55d0b
commit 8d899925dc
3 changed files with 22 additions and 6 deletions
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7
src/hotspot/cpu/x86/vm_version_x86.cpp
View File

@@ -2079,11 +2079,14 @@ bool VM_Version::is_default_intel_cascade_lake() {
return FLAG_IS_DEFAULT(UseAVX) &&
FLAG_IS_DEFAULT(MaxVectorSize) &&
UseAVX > 2 &&
is_intel_skylake() &&
_stepping >= 5;
is_intel_cascade_lake();
}
#endif
bool VM_Version::is_intel_cascade_lake() {
return is_intel_skylake() && _stepping >= 5;
}
// avx3_threshold() sets the threshold at which 64-byte instructions are used
// for implementing the array copy and clear operations.
// The Intel platforms that supports the serialize instruction

2
src/hotspot/cpu/x86/vm_version_x86.hpp
View File

@@ -716,6 +716,8 @@ public:
static bool is_default_intel_cascade_lake();
#endif
static bool is_intel_cascade_lake();
static int avx3_threshold();
static bool is_intel_tsc_synched_at_init();

19
src/hotspot/cpu/x86/x86_64.ad
View File

@@ -13732,6 +13732,13 @@ instruct leaL_rReg_immI2_peep(rRegL dst, rRegL src, immI2 shift)
ins_pipe(ialu_reg_reg);
%}
// These peephole rules replace mov + I pairs (where I is one of {add, inc, dec,
// sal}) with lea instructions. The {add, sal} rules are beneficial in
// processors with at least partial ALU support for lea
// (supports_fast_2op_lea()), whereas the {inc, dec} rules are only generally
// beneficial for processors with full ALU support
// (VM_Version::supports_fast_3op_lea()) and Intel Cascade Lake.
peephole
%{
peeppredicate(VM_Version::supports_fast_2op_lea());
@@ -13750,7 +13757,8 @@ peephole
peephole
%{
peeppredicate(VM_Version::supports_fast_2op_lea());
peeppredicate(VM_Version::supports_fast_3op_lea() ||
VM_Version::is_intel_cascade_lake());
peepmatch (incI_rReg);
peepprocedure (lea_coalesce_imm);
peepreplace (leaI_rReg_immI_peep());
@@ -13758,7 +13766,8 @@ peephole
peephole
%{
peeppredicate(VM_Version::supports_fast_2op_lea());
peeppredicate(VM_Version::supports_fast_3op_lea() ||
VM_Version::is_intel_cascade_lake());
peepmatch (decI_rReg);
peepprocedure (lea_coalesce_imm);
peepreplace (leaI_rReg_immI_peep());
@@ -13790,7 +13799,8 @@ peephole
peephole
%{
peeppredicate(VM_Version::supports_fast_2op_lea());
peeppredicate(VM_Version::supports_fast_3op_lea() ||
VM_Version::is_intel_cascade_lake());
peepmatch (incL_rReg);
peepprocedure (lea_coalesce_imm);
peepreplace (leaL_rReg_immL32_peep());
@@ -13798,7 +13808,8 @@ peephole
peephole
%{
peeppredicate(VM_Version::supports_fast_2op_lea());
peeppredicate(VM_Version::supports_fast_3op_lea() ||
VM_Version::is_intel_cascade_lake());
peepmatch (decL_rReg);
peepprocedure (lea_coalesce_imm);
peepreplace (leaL_rReg_immL32_peep());