Revert "8294160: misc crash dump improvements"

This reverts commit 8dd1056831.

.github/workflows/build-windows.yml

@@ -92,26 +92,12 @@ jobs:
         id: gtest
         uses: ./.github/actions/get-gtest
 
-      - name: 'Check toolchain installed'
-        id: toolchain-check
-        run: |
-          set +e
-          '/c/Program Files (x86)/Microsoft Visual Studio/2019/Enterprise/vc/auxiliary/build/vcvars64.bat' -vcvars_ver=${{ inputs.msvc-toolset-version }}
-          if [ $? -eq 0 ]; then
-            echo "Toolchain is already installed"
-            echo "toolchain-installed=true" >> $GITHUB_OUTPUT
-          else
-            echo "Toolchain is not yet installed"
-            echo "toolchain-installed=false" >> $GITHUB_OUTPUT
-          fi
-
       - name: 'Install toolchain and dependencies'
         run: |
           # Run Visual Studio Installer
           '/c/Program Files (x86)/Microsoft Visual Studio/Installer/vs_installer.exe' \
-            modify --quiet --installPath 'C:\Program Files (x86)\Microsoft Visual Studio\2019\Enterprise' \
+            modify --quiet --installPath 'C:/Program Files (x86)/Microsoft Visual Studio/2019/Enterprise' \
             --add Microsoft.VisualStudio.Component.VC.${{ inputs.msvc-toolset-version }}.${{ inputs.msvc-toolset-architecture }}
-        if: steps.toolchain-check.outputs.toolchain-installed != 'true'
 
       - name: 'Configure'
         run: >

.github/workflows/main.yml

@@ -223,7 +223,7 @@ jobs:
     uses: ./.github/workflows/build-windows.yml
     with:
       platform: windows-x64
-      msvc-toolset-version: '14.29'
+      msvc-toolset-version: '14.25'
       msvc-toolset-architecture: 'x86.x64'
     if: needs.select.outputs.windows-x64 == 'true'
 

.gitignore

@@ -18,7 +18,5 @@ NashornProfile.txt
 /src/utils/LogCompilation/target/
 /.project/
 /.settings/
-/compile_commands.json
-/.cache
 *.class
 .idea/workspace.xml

.jcheck/conf

@@ -1,7 +1,7 @@
 [general]
 project=jdk-updates
 jbs=JDK
-version=17.0.8
+version=17.0.7
 
 [checks]
 error=author,committer,reviewers,merge,issues,executable,symlink,message,hg-tag,whitespace,problemlists

bin/jib.sh

@@ -128,15 +128,6 @@ install_jib() {
             exit 1
         fi
     fi
-    # Want to check the filetype using file, to see if we got served a HTML error page.
-    # This is sensitive to the filename containing a specific string, but good enough.
-    file "${installed_jib_script}.gz" | grep "gzip compressed data" > /dev/null
-    if [ $? -ne 0 ]; then 
-        echo "Warning: ${installed_jib_script}.gz is not a gzip file."
-        echo "If you are behind a proxy you may need to configure exceptions using no_proxy."
-        echo "The download URL was: ${jib_url}"
-        exit 1
-    fi
     echo "Extracting JIB bootstrap script"
     rm -f "${installed_jib_script}"
     gunzip "${installed_jib_script}.gz"

doc/building.html

@@ -274,7 +274,7 @@
 <tbody>
 <tr class="odd">
 <td>Linux</td>
-<td>gcc 11.2.0</td>
+<td>gcc 10.2.0</td>
 </tr>
 <tr class="even">
 <td>macOS</td>
@@ -289,7 +289,7 @@
 <p>All compilers are expected to be able to compile to the C99 language standard, as some C99 features are used in the source code. Microsoft Visual Studio doesn't fully support C99 so in practice shared code is limited to using C99 features that it does support.</p>
 <h3 id="gcc">gcc</h3>
 <p>The minimum accepted version of gcc is 5.0. Older versions will generate a warning by <code>configure</code> and are unlikely to work.</p>
-<p>The JDK is currently known to be able to compile with at least version 11.2 of gcc.</p>
+<p>The JDK is currently known to be able to compile with at least version 10.2 of gcc.</p>
 <p>In general, any version between these two should be usable.</p>
 <h3 id="clang">clang</h3>
 <p>The minimum accepted version of clang is 3.5. Older versions will not be accepted by <code>configure</code>.</p>

doc/building.md

@@ -321,7 +321,7 @@ issues.
 
 | Operating system   | Toolchain version                          |
 | ------------------ | ------------------------------------------ |
-| Linux              | gcc 11.2.0                                 |
+| Linux              | gcc 10.2.0                                 |
 | macOS              | Apple Xcode 10.1 (using clang 10.0.0)      |
 | Windows            | Microsoft Visual Studio 2022 update 17.1.0 |
 
@@ -335,7 +335,7 @@ features that it does support.
 The minimum accepted version of gcc is 5.0. Older versions will generate a warning
 by `configure` and are unlikely to work.
 
-The JDK is currently known to be able to compile with at least version 11.2 of
+The JDK is currently known to be able to compile with at least version 10.2 of
 gcc.
 
 In general, any version between these two should be usable.

doc/testing.html

@@ -242,39 +242,14 @@ $ make test JTREG="VM_OPTIONS=-Duser.language=en -Duser.country=US" TE
     JTREG=&quot;JAVA_OPTIONS=-Dtest.nss.lib.paths=/path/to/your/latest/NSS-libs&quot;</code></pre>
 <p>For more notes about the PKCS11 tests, please refer to test/jdk/sun/security/pkcs11/README.</p>
 <h3 id="client-ui-tests">Client UI Tests</h3>
-<h4 id="system-key-shortcuts">System key shortcuts</h4>
 <p>Some Client UI tests use key sequences which may be reserved by the operating system. Usually that causes the test failure. So it is highly recommended to disable system key shortcuts prior testing. The steps to access and disable system key shortcuts for various platforms are provided below.</p>
-<h5 id="macos">MacOS</h5>
+<h4 id="macos">MacOS</h4>
 <p>Choose Apple menu; System Preferences, click Keyboard, then click Shortcuts; select or deselect desired shortcut.</p>
 <p>For example, test/jdk/javax/swing/TooltipManager/JMenuItemToolTipKeyBindingsTest/JMenuItemToolTipKeyBindingsTest.java fails on MacOS because it uses <code>CTRL + F1</code> key sequence to show or hide tooltip message but the key combination is reserved by the operating system. To run the test correctly the default global key shortcut should be disabled using the steps described above, and then deselect &quot;Turn keyboard access on or off&quot; option which is responsible for <code>CTRL + F1</code> combination.</p>
-<h5 id="linux">Linux</h5>
+<h4 id="linux">Linux</h4>
 <p>Open the Activities overview and start typing Settings; Choose Settings, click Devices, then click Keyboard; set or override desired shortcut.</p>
-<h5 id="windows">Windows</h5>
+<h4 id="windows">Windows</h4>
 <p>Type <code>gpedit</code> in the Search and then click Edit group policy; navigate to User Configuration -&gt; Administrative Templates -&gt; Windows Components -&gt; File Explorer; in the right-side pane look for &quot;Turn off Windows key hotkeys&quot; and double click on it; enable or disable hotkeys.</p>
 <p>Note: restart is required to make the settings take effect.</p>
-<h4 id="robot-api">Robot API</h4>
-<p>Most automated Client UI tests use <code>Robot</code> API to control
-the UI. Usually, the default operating system settings need to be
-adjusted for Robot to work correctly. The detailed steps how to access
-and update these settings for different platforms are provided
-below.</p>
-<h5 id="macos-1">macOS</h5>
-<p><code>Robot</code> is not permitted to control your Mac by default
-since macOS 10.15. To allow it, choose Apple menu -&gt; System Settings,
-click Privacy &amp; Security; then click Accessibility and ensure the
-following apps are allowed to control your computer: <em>Java</em> and
-<em>Terminal</em>. If the tests are run from an IDE, the IDE should be
-granted this permission too.</p>
-<h5 id="windows-1">Windows</h5>
-<p>On Windows if Cygwin terminal is used to run the tests, there is a
-delay in focus transfer. Usually it causes automated UI test failure. To
-disable the delay, type <code>regedit</code> in the Search and then
-select Registry Editor; navigate to the following key:
-<code>HKEY_CURRENT_USER\Control Panel\Desktop</code>; make sure the
-<code>ForegroundLockTimeout</code> value is set to 0.</p>
-<p>Additional information about Client UI tests configuration for
-various operating systems can be obtained at <a
-href="https://wiki.openjdk.org/display/ClientLibs/Automated+client+GUI+testing+system+set+up+requirements">Automated
-client GUI testing system set up requirements</a></p>
 </body>
 </html>

doc/testing.md

@@ -546,14 +546,12 @@ test/jdk/sun/security/pkcs11/README.
 
 ### Client UI Tests
 
-#### System key shortcuts
-
 Some Client UI tests use key sequences which may be reserved by the operating
 system. Usually that causes the test failure. So it is highly recommended to
 disable system key shortcuts prior testing. The steps to access and disable
 system key shortcuts for various platforms are provided below.
 
-##### macOS
+#### MacOS
 
 Choose Apple menu; System Preferences, click Keyboard, then click Shortcuts;
 select or deselect desired shortcut.
@@ -566,12 +564,12 @@ test correctly the default global key shortcut should be disabled using the
 steps described above, and then deselect "Turn keyboard access on or off"
 option which is responsible for `CTRL + F1` combination.
 
-##### Linux
+#### Linux
 
 Open the Activities overview and start typing Settings; Choose Settings, click
 Devices, then click Keyboard; set or override desired shortcut.
 
-##### Windows
+#### Windows
 
 Type `gpedit` in the Search and then click Edit group policy; navigate to User
 Configuration -> Administrative Templates -> Windows Components -> File
@@ -580,33 +578,6 @@ double click on it; enable or disable hotkeys.
 
 Note: restart is required to make the settings take effect.
 
-#### Robot API
-
-Most automated Client UI tests use `Robot` API to control the UI. Usually,
-the default operating system settings need to be adjusted for Robot
-to work correctly. The detailed steps how to access and update these settings
-for different platforms are provided below.
-
-##### macOS
-
-`Robot` is not permitted to control your Mac by default since
-macOS 10.15. To allow it, choose Apple menu -> System Settings, click
-Privacy & Security; then click Accessibility and ensure the following apps are
-allowed to control your computer: *Java* and *Terminal*. If the tests are run
-from an IDE, the IDE should be granted this permission too.
-
-##### Windows
-
-On Windows if Cygwin terminal is used to run the tests, there is a delay in
-focus transfer. Usually it causes automated UI test failure. To disable the
-delay, type `regedit` in the Search and then select Registry Editor; navigate
-to the following key: `HKEY_CURRENT_USER\Control Panel\Desktop`; make sure
-the `ForegroundLockTimeout` value is set to 0.
-
-Additional information about Client UI tests configuration for various operating
-systems can be obtained at [Automated client GUI testing system set up
-requirements](https://wiki.openjdk.org/display/ClientLibs/Automated+client+GUI+testing+system+set+up+requirements)
-
 ---
 # Override some definitions in the global css file that are not optimal for
 # this document.

make/ReleaseFile.gmk

@@ -51,7 +51,6 @@ define create-info-file
   $(if $(VENDOR_VERSION_STRING), \
     $(call info-file-item, "IMPLEMENTOR_VERSION", "$(VENDOR_VERSION_STRING)"))
   $(call info-file-item, "JAVA_VERSION_DATE", "$(VERSION_DATE)")
-  $(call info-file-item, "JAVA_RUNTIME_VERSION", "$(VERSION_STRING)")
   $(call info-file-item, "OS_NAME", "$(RELEASE_FILE_OS_NAME)")
   $(call info-file-item, "OS_ARCH", "$(RELEASE_FILE_OS_ARCH)")
   $(call info-file-item, "LIBC", "$(RELEASE_FILE_LIBC)")

make/autoconf/basic.m4

@@ -55,7 +55,6 @@ AC_DEFUN([BASIC_CHECK_LEFTOVER_OVERRIDDEN],
 
 ###############################################################################
 # Setup basic configuration paths, and platform-specific stuff related to PATHs.
-# Make sure to only use tools set up in BASIC_SETUP_FUNDAMENTAL_TOOLS.
 AC_DEFUN_ONCE([BASIC_SETUP_PATHS],
 [
   # Save the current directory this script was started from

make/autoconf/basic_tools.m4

@@ -24,8 +24,8 @@
 #
 
 ###############################################################################
-# Setup the most fundamental tools, used for setting up build platform and
-# path handling.
+# Setup the most fundamental tools that relies on not much else to set up,
+# but is used by much of the early bootstrap code.
 AC_DEFUN_ONCE([BASIC_SETUP_FUNDAMENTAL_TOOLS],
 [
   # Bootstrapping: These tools are needed by UTIL_LOOKUP_PROGS
@@ -37,28 +37,7 @@ AC_DEFUN_ONCE([BASIC_SETUP_FUNDAMENTAL_TOOLS],
   UTIL_CHECK_NONEMPTY(FILE)
   AC_PATH_PROGS(LDD, ldd)
 
-  # Required tools
-  UTIL_REQUIRE_PROGS(ECHO, echo)
-  UTIL_REQUIRE_PROGS(TR, tr)
-  UTIL_REQUIRE_PROGS(UNAME, uname)
-  UTIL_REQUIRE_PROGS(WC, wc)
-
-  # Required tools with some special treatment
-  UTIL_REQUIRE_SPECIAL(GREP, [AC_PROG_GREP])
-  UTIL_REQUIRE_SPECIAL(EGREP, [AC_PROG_EGREP])
-  UTIL_REQUIRE_SPECIAL(SED, [AC_PROG_SED])
-
-  # Tools only needed on some platforms
-  UTIL_LOOKUP_PROGS(PATHTOOL, cygpath wslpath)
-  UTIL_LOOKUP_PROGS(CMD, cmd.exe, $PATH:/cygdrive/c/windows/system32:/mnt/c/windows/system32:/c/windows/system32)
-])
-
-###############################################################################
-# Setup further tools that should be resolved early but after setting up
-# build platform and path handling.
-AC_DEFUN_ONCE([BASIC_SETUP_TOOLS],
-[
-  # Required tools
+  # First are all the fundamental required tools.
   UTIL_REQUIRE_PROGS(BASH, bash)
   UTIL_REQUIRE_PROGS(CAT, cat)
   UTIL_REQUIRE_PROGS(CHMOD, chmod)
@@ -66,6 +45,7 @@ AC_DEFUN_ONCE([BASIC_SETUP_TOOLS],
   UTIL_REQUIRE_PROGS(CUT, cut)
   UTIL_REQUIRE_PROGS(DATE, date)
   UTIL_REQUIRE_PROGS(DIFF, gdiff diff)
+  UTIL_REQUIRE_PROGS(ECHO, echo)
   UTIL_REQUIRE_PROGS(EXPR, expr)
   UTIL_REQUIRE_PROGS(FIND, find)
   UTIL_REQUIRE_PROGS(GUNZIP, gunzip)
@@ -87,18 +67,26 @@ AC_DEFUN_ONCE([BASIC_SETUP_TOOLS],
   UTIL_REQUIRE_PROGS(TAR, gtar tar)
   UTIL_REQUIRE_PROGS(TEE, tee)
   UTIL_REQUIRE_PROGS(TOUCH, touch)
+  UTIL_REQUIRE_PROGS(TR, tr)
+  UTIL_REQUIRE_PROGS(UNAME, uname)
+  UTIL_REQUIRE_PROGS(WC, wc)
   UTIL_REQUIRE_PROGS(XARGS, xargs)
 
-  # Required tools with some special treatment
+  # Then required tools that require some special treatment.
+  UTIL_REQUIRE_SPECIAL(GREP, [AC_PROG_GREP])
+  UTIL_REQUIRE_SPECIAL(EGREP, [AC_PROG_EGREP])
   UTIL_REQUIRE_SPECIAL(FGREP, [AC_PROG_FGREP])
+  UTIL_REQUIRE_SPECIAL(SED, [AC_PROG_SED])
 
   # Optional tools, we can do without them
   UTIL_LOOKUP_PROGS(DF, df)
   UTIL_LOOKUP_PROGS(NICE, nice)
   UTIL_LOOKUP_PROGS(READLINK, greadlink readlink)
 
-  # Tools only needed on some platforms
+  # These are only needed on some platforms
+  UTIL_LOOKUP_PROGS(PATHTOOL, cygpath wslpath)
   UTIL_LOOKUP_PROGS(LSB_RELEASE, lsb_release)
+  UTIL_LOOKUP_PROGS(CMD, cmd.exe, $PATH:/cygdrive/c/windows/system32:/mnt/c/windows/system32:/c/windows/system32)
 
   # For compare.sh only
   UTIL_LOOKUP_PROGS(CMP, cmp)

make/autoconf/build-aux/config.sub

@@ -1,6 +1,6 @@
 #!/bin/sh
 #
-# Copyright (c) 2014, 2022, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2014, 2020, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -46,13 +46,6 @@ if echo $* | grep pc-msys >/dev/null ; then
     exit
 fi
 
-# Canonicalize for riscv which autoconf-config.sub doesn't handle
-if echo $* | grep '^riscv\(32\|64\)-linux' >/dev/null ; then
-    result=`echo $@ | sed 's/linux/unknown-linux/'`
-    echo $result
-    exit
-fi
-
 # Filter out everything that doesn't begin with "aarch64-"
 if ! echo $* | grep '^aarch64-' >/dev/null ; then
     . $DIR/autoconf-config.sub "$@"
@@ -85,3 +78,4 @@ result=`echo $result | sed "s/^arm-/aarch64-/"`
 
 echo $result
 exit $exitcode
+

make/autoconf/configure.ac

@@ -86,7 +86,6 @@ PLATFORM_SETUP_OPENJDK_BUILD_AND_TARGET
 
 # Continue setting up basic stuff. Most remaining code require fundamental tools.
 BASIC_SETUP_PATHS
-BASIC_SETUP_TOOLS
 
 # Check if it's a pure open build or if custom sources are to be used.
 JDKOPT_SETUP_OPEN_OR_CUSTOM

make/autoconf/flags-cflags.m4

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2023, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -188,10 +188,6 @@ AC_DEFUN([FLAGS_SETUP_WARNINGS],
       WARNINGS_ENABLE_ALL_CXXFLAGS="$WARNINGS_ENABLE_ALL_CFLAGS $WARNINGS_ENABLE_ADDITIONAL_CXX"
 
       DISABLED_WARNINGS="unused-parameter unused"
-      # gcc10/11 on ppc generate lots of abi warnings about layout of aggregates containing vectors
-      if test "x$OPENJDK_TARGET_CPU_ARCH" = "xppc"; then
-        DISABLED_WARNINGS="$DISABLED_WARNINGS psabi"
-      fi
       ;;
 
     clang)

make/autoconf/jvm-features.m4

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2023, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -248,11 +248,8 @@ AC_DEFUN_ONCE([JVM_FEATURES_CHECK_CDS],
 AC_DEFUN_ONCE([JVM_FEATURES_CHECK_DTRACE],
 [
   JVM_FEATURES_CHECK_AVAILABILITY(dtrace, [
-    AC_MSG_CHECKING([for dtrace tool and platform support])
-    if test "x$OPENJDK_TARGET_CPU_ARCH" = "xppc"; then
-      AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU_ARCH])
-      AVAILABLE=false
-    elif test "x$DTRACE" != "x" && test -x "$DTRACE"; then
+    AC_MSG_CHECKING([for dtrace tool])
+    if test "x$DTRACE" != "x" && test -x "$DTRACE"; then
       AC_MSG_RESULT([$DTRACE])
     else
       AC_MSG_RESULT([no])
@@ -311,8 +308,7 @@ AC_DEFUN_ONCE([JVM_FEATURES_CHECK_SHENANDOAHGC],
     AC_MSG_CHECKING([if platform is supported by Shenandoah])
     if test "x$OPENJDK_TARGET_CPU_ARCH" = "xx86" || \
         test "x$OPENJDK_TARGET_CPU" = "xaarch64" || \
-        test "x$OPENJDK_TARGET_CPU" = "xppc64le" || \
-        test "x$OPENJDK_TARGET_CPU" = "xriscv64"; then
+        test "x$OPENJDK_TARGET_CPU" = "xppc64le"; then
       AC_MSG_RESULT([yes])
     else
       AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU])
@@ -362,8 +358,7 @@ AC_DEFUN_ONCE([JVM_FEATURES_CHECK_ZGC],
         AC_MSG_RESULT([no, $OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU])
         AVAILABLE=false
       fi
-    elif test "x$OPENJDK_TARGET_CPU" = "xppc64le" || \
-        test "x$OPENJDK_TARGET_CPU" = "xriscv64"; then
+    elif test "x$OPENJDK_TARGET_CPU" = "xppc64le"; then
       if test "x$OPENJDK_TARGET_OS" = "xlinux"; then
         AC_MSG_RESULT([yes])
       else

make/autoconf/libraries.m4

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2022, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -160,12 +160,6 @@ AC_DEFUN_ONCE([LIB_SETUP_LIBRARIES],
     fi
   fi
 
-  # Because RISC-V only has word-sized atomics, it requries libatomic where
-  # other common architectures do not.  So link libatomic by default.
-  if test "x$OPENJDK_TARGET_OS" = xlinux && test "x$OPENJDK_TARGET_CPU" = xriscv64; then
-    BASIC_JVM_LIBS="$BASIC_JVM_LIBS -latomic"
-  fi
-
   # perfstat lib
   if test "x$OPENJDK_TARGET_OS" = xaix; then
     BASIC_JVM_LIBS="$BASIC_JVM_LIBS -lperfstat"
@@ -173,7 +167,7 @@ AC_DEFUN_ONCE([LIB_SETUP_LIBRARIES],
 
   if test "x$OPENJDK_TARGET_OS" = xwindows; then
     BASIC_JVM_LIBS="$BASIC_JVM_LIBS kernel32.lib user32.lib gdi32.lib winspool.lib \
-        comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib powrprof.lib uuid.lib \
+        comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib \
         wsock32.lib winmm.lib version.lib psapi.lib"
   fi
 

make/autoconf/platform.m4

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2022, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -561,8 +561,6 @@ AC_DEFUN([PLATFORM_SETUP_LEGACY_VARS_HELPER],
     HOTSPOT_$1_CPU_DEFINE=PPC64
   elif test "x$OPENJDK_$1_CPU" = xppc64le; then
     HOTSPOT_$1_CPU_DEFINE=PPC64
-  elif test "x$OPENJDK_$1_CPU" = xriscv64; then
-    HOTSPOT_$1_CPU_DEFINE=RISCV64
 
   # The cpu defines below are for zero, we don't support them directly.
   elif test "x$OPENJDK_$1_CPU" = xsparc; then
@@ -573,6 +571,8 @@ AC_DEFUN([PLATFORM_SETUP_LEGACY_VARS_HELPER],
     HOTSPOT_$1_CPU_DEFINE=S390
   elif test "x$OPENJDK_$1_CPU" = xs390x; then
     HOTSPOT_$1_CPU_DEFINE=S390
+  elif test "x$OPENJDK_$1_CPU" = xriscv64; then
+    HOTSPOT_$1_CPU_DEFINE=RISCV
   elif test "x$OPENJDK_$1_CPU" != x; then
     HOTSPOT_$1_CPU_DEFINE=$(echo $OPENJDK_$1_CPU | tr a-z A-Z)
   fi
@@ -632,7 +632,6 @@ AC_DEFUN([PLATFORM_SET_MODULE_TARGET_OS_VALUES],
 ])
 
 #%%% Build and target systems %%%
-# Make sure to only use tools set up in BASIC_SETUP_FUNDAMENTAL_TOOLS.
 AC_DEFUN_ONCE([PLATFORM_SETUP_OPENJDK_BUILD_AND_TARGET],
 [
   # Figure out the build and target systems. # Note that in autoconf terminology, "build" is obvious, but "target"
@@ -719,7 +718,7 @@ AC_DEFUN_ONCE([PLATFORM_SETUP_OPENJDK_TARGET_ENDIANNESS],
 [
   ###############################################################################
   #
-  # Is the target little or big endian?
+  # Is the target little of big endian?
   #
   AC_C_BIGENDIAN([ENDIAN="big"],[ENDIAN="little"],[ENDIAN="unknown"],[ENDIAN="universal_endianness"])
 

make/common/NativeCompilation.gmk

@@ -343,15 +343,10 @@ define SetupCompileNativeFileBody
       endif
     endif
 
-    ifneq ($(DISABLE_WARNING_PREFIX), )
-      $1_WARNINGS_FLAGS := $$(addprefix $(DISABLE_WARNING_PREFIX), \
-        $$($$($1_BASE)_DISABLED_WARNINGS_$(TOOLCHAIN_TYPE)_$$($1_FILENAME)))
-    endif
-
     $1_BASE_CFLAGS :=  $$($$($1_BASE)_CFLAGS) $$($$($1_BASE)_EXTRA_CFLAGS) \
-        $$($$($1_BASE)_SYSROOT_CFLAGS) $$($1_WARNINGS_FLAGS)
+        $$($$($1_BASE)_SYSROOT_CFLAGS)
     $1_BASE_CXXFLAGS := $$($$($1_BASE)_CXXFLAGS) $$($$($1_BASE)_EXTRA_CXXFLAGS) \
-        $$($$($1_BASE)_SYSROOT_CFLAGS) $$($1_EXTRA_CXXFLAGS) $$($1_WARNINGS_FLAGS)
+        $$($$($1_BASE)_SYSROOT_CFLAGS) $$($1_EXTRA_CXXFLAGS)
     $1_BASE_ASFLAGS := $$($$($1_BASE)_ASFLAGS) $$($$($1_BASE)_EXTRA_ASFLAGS)
 
     ifneq ($$(filter %.c, $$($1_FILENAME)), )

make/conf/jib-profiles.js

@@ -1048,10 +1048,10 @@ var getJibProfilesProfiles = function (input, common, data) {
 var getJibProfilesDependencies = function (input, common) {
 
     var devkit_platform_revisions = {
-        linux_x64: "gcc11.2.0-OL6.4+1.0",
+        linux_x64: "gcc10.3.0-OL6.4+1.0",
         macosx: "Xcode12.4+1.0",
         windows_x64: "VS2022-17.1.0+1.0",
-        linux_aarch64: "gcc11.2.0-OL7.6+1.0",
+        linux_aarch64: "gcc10.3.0-OL7.6+1.0",
         linux_arm: "gcc8.2.0-Fedora27+1.0",
         linux_ppc64le: "gcc8.2.0-Fedora27+1.0",
         linux_s390x: "gcc8.2.0-Fedora27+1.0"

make/conf/version-numbers.conf

@@ -28,12 +28,12 @@
 
 DEFAULT_VERSION_FEATURE=17
 DEFAULT_VERSION_INTERIM=0
-DEFAULT_VERSION_UPDATE=8
+DEFAULT_VERSION_UPDATE=7
 DEFAULT_VERSION_PATCH=0
 DEFAULT_VERSION_EXTRA1=0
 DEFAULT_VERSION_EXTRA2=0
 DEFAULT_VERSION_EXTRA3=0
-DEFAULT_VERSION_DATE=2023-07-18
+DEFAULT_VERSION_DATE=2023-04-18
 DEFAULT_VERSION_CLASSFILE_MAJOR=61  # "`$EXPR $DEFAULT_VERSION_FEATURE + 44`"
 DEFAULT_VERSION_CLASSFILE_MINOR=0
 DEFAULT_VERSION_DOCS_API_SINCE=11

make/data/cacerts/gtsrootcar1

@@ -1,38 +0,0 @@
-Owner: CN=GTS Root R1, O=Google Trust Services LLC, C=US
-Issuer: CN=GTS Root R1, O=Google Trust Services LLC, C=US
-Serial number: 203e5936f31b01349886ba217
-Valid from: Wed Jun 22 00:00:00 GMT 2016 until: Sun Jun 22 00:00:00 GMT 2036
-Signature algorithm name: SHA384withRSA
-Subject Public Key Algorithm: 4096-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
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-6u9AWpQKXCBfTkBdYiJ23//OYb2MI3jSNwLgjt7RETeJ9r/tSQdirpLsQBqvFAnZ
-0E6yove+7u7Y/9waLd64NnHi/Hm3lCXRSHNboTXns5lndcEZOitHTtNCjv0xyBZm
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-bP6MvPJwNQzcmRk13NfIRmPVNnGuV/u3gm3c
------END CERTIFICATE-----

make/data/cacerts/gtsrootcar2

@@ -1,38 +0,0 @@
-Owner: CN=GTS Root R2, O=Google Trust Services LLC, C=US
-Issuer: CN=GTS Root R2, O=Google Trust Services LLC, C=US
-Serial number: 203e5aec58d04251aab1125aa
-Valid from: Wed Jun 22 00:00:00 GMT 2016 until: Sun Jun 22 00:00:00 GMT 2036
-Signature algorithm name: SHA384withRSA
-Subject Public Key Algorithm: 4096-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
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-HyICc/sgCq+dVEuhzf9gR7A/Xe8bVr2XIZYtCtFenTgCR2y59PYjJbigapordwj6
-xLEokCZYCDzifqrXPW+6MYgKBesntaFJ7qBFVHvmJ2WZICGoo7z7GJa7Um8M7YNR
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-6WLAYv7YTVWW4tAR+kg0Eeye7QUd5MjWHYbL
------END CERTIFICATE-----

make/data/cacerts/gtsrootecccar3

@@ -1,20 +0,0 @@
-Owner: CN=GTS Root R3, O=Google Trust Services LLC, C=US
-Issuer: CN=GTS Root R3, O=Google Trust Services LLC, C=US
-Serial number: 203e5b882eb20f825276d3d66
-Valid from: Wed Jun 22 00:00:00 GMT 2016 until: Sun Jun 22 00:00:00 GMT 2036
-Signature algorithm name: SHA384withECDSA
-Subject Public Key Algorithm: 384-bit EC (secp384r1) key
-Version: 3
------BEGIN CERTIFICATE-----
-MIICCTCCAY6gAwIBAgINAgPluILrIPglJ209ZjAKBggqhkjOPQQDAzBHMQswCQYD
-VQQGEwJVUzEiMCAGA1UEChMZR29vZ2xlIFRydXN0IFNlcnZpY2VzIExMQzEUMBIG
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------END CERTIFICATE-----

make/data/cacerts/gtsrootecccar4

@@ -1,20 +0,0 @@
-Owner: CN=GTS Root R4, O=Google Trust Services LLC, C=US
-Issuer: CN=GTS Root R4, O=Google Trust Services LLC, C=US
-Serial number: 203e5c068ef631a9c72905052
-Valid from: Wed Jun 22 00:00:00 GMT 2016 until: Sun Jun 22 00:00:00 GMT 2036
-Signature algorithm name: SHA384withECDSA
-Subject Public Key Algorithm: 384-bit EC (secp384r1) key
-Version: 3
------BEGIN CERTIFICATE-----
-MIICCTCCAY6gAwIBAgINAgPlwGjvYxqccpBQUjAKBggqhkjOPQQDAzBHMQswCQYD
-VQQGEwJVUzEiMCAGA1UEChMZR29vZ2xlIFRydXN0IFNlcnZpY2VzIExMQzEUMBIG
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------END CERTIFICATE-----

make/data/cacerts/microsoftecc2017

@@ -1,22 +0,0 @@
-Owner: CN=Microsoft ECC Root Certificate Authority 2017, O=Microsoft Corporation, C=US
-Issuer: CN=Microsoft ECC Root Certificate Authority 2017, O=Microsoft Corporation, C=US
-Serial number: 66f23daf87de8bb14aea0c573101c2ec
-Valid from: Wed Dec 18 23:06:45 GMT 2019 until: Fri Jul 18 23:16:04 GMT 2042
-Signature algorithm name: SHA384withECDSA
-Subject Public Key Algorithm: 384-bit EC (secp384r1) key
-Version: 3
------BEGIN CERTIFICATE-----
-MIICWTCCAd+gAwIBAgIQZvI9r4fei7FK6gxXMQHC7DAKBggqhkjOPQQDAzBlMQsw
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------END CERTIFICATE-----

make/data/cacerts/microsoftrsa2017

@@ -1,40 +0,0 @@
-Owner: CN=Microsoft RSA Root Certificate Authority 2017, O=Microsoft Corporation, C=US
-Issuer: CN=Microsoft RSA Root Certificate Authority 2017, O=Microsoft Corporation, C=US
-Serial number: 1ed397095fd8b4b347701eaabe7f45b3
-Valid from: Wed Dec 18 22:51:22 GMT 2019 until: Fri Jul 18 23:00:23 GMT 2042
-Signature algorithm name: SHA384withRSA
-Subject Public Key Algorithm: 4096-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
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------END CERTIFICATE-----

make/data/cacerts/twcaglobalrootca

@@ -1,38 +0,0 @@
-Owner: CN=TWCA Global Root CA, OU=Root CA, O=TAIWAN-CA, C=TW
-Issuer: CN=TWCA Global Root CA, OU=Root CA, O=TAIWAN-CA, C=TW
-Serial number: cbe
-Valid from: Wed Jun 27 06:28:33 GMT 2012 until: Tue Dec 31 15:59:59 GMT 2030
-Signature algorithm name: SHA256withRSA
-Subject Public Key Algorithm: 4096-bit RSA key
-Version: 3
------BEGIN CERTIFICATE-----
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-SIb3DQEBAQUAA4ICDwAwggIKAoICAQCwBdvI64zEbooh745NnHEKH1Jw7W2CnJfF
-10xORUnLQEK1EjRsGcJ0pDFfhQKX7EMzClPSnIyOt7h52yvVavKOZsTuKwEHktSz
-0ALfUPZVr2YOy+BHYC8rMjk1Ujoog/h7FsYYuGLWRyWRzvAZEk2tY/XTP3VfKfCh
-MBwqoJimFb3u/Rk28OKRQ4/6ytYQJ0lM793B8YVwm8rqqFpD/G2Gb3PpN0Wp8DbH
-zIh1HrtsBv+baz4X7GGqcXzGHaL3SekVtTzWoWH1EfcFbx39Eb7QMAfCKbAJTibc
-46KokWofwpFFiFzlmLhxpRUZyXx1EcxwdE8tmx2RRP1WKKD+u4ZqyPpcC1jcxkt2
-yKsi2XMPpfRaAok/T54igu6idFMqPVMnaR1sjjIsZAAmY2E2TqNGtz99sy2sbZCi
-laLOz9qC5wc0GZbpuCGqKX6mOL6OKUohZnkfs8O1CWfe1tQHRvMq2uYiN2DLgbYP
-oA/pyJV/v1WRBXrPPRXAb94JlAGD1zQbzECl8LibZ9WYkTunhHiVJqRaCPgrdLQA
-BDzfuBSO6N+pjWxnkjMdwLfS7JLIvgm/LCkFbwJrnu+8vyq8W8BQj0FwcYeyTbcE
-qYSjMq+u7msXi7Kx/mzhkIyIqJdIzshNy/MGz19qCkKxHh53L46g5pIOBvwFItIm
-4TFRfTLcDwIDAQABoyMwITAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB
-/zANBgkqhkiG9w0BAQsFAAOCAgEAXzSBdu+WHdXltdkCY4QWwa6gcFGn90xHNcgL
-1yg9iXHZqjNB6hQbbCEAwGxCGX6faVsgQt+i0trEfJdLjbDorMjupWkEmQqSpqsn
-LhpNgb+E1HAerUf+/UqdM+DyucRFCCEK2mlpc3INvjT+lIutwx4116KD7+U4x6WF
-H6vPNOw/KP4M8VeGTslV9xzU2KV9Bnpv1d8Q34FOIWWxtuEXeZVFBs5fzNxGiWNo
-RI2T9GRwoD2dKAXDOXC4Ynsg/eTb6QihuJ49CcdP+yz4k3ZB3lLg4VfSnQO8d57+
-nile98FRYB/e2guyLXW3Q0iT5/Z5xoRdgFlglPx4mI88k1HtQJAH32RjJMtOcQWh
-15QaiDLxInQirqWm2BJpTGCjAu4r7NRjkgtevi92a6O2JryPA9gK8kxkRr05YuWW
-6zRjESjMlfGt7+/cgFhI6Uu46mWs6fyAtbXIRfmswZ/ZuepiiI7E8UuDEq3mi4TW
-nsLrgxifarsbJGAzcMzs9zLzXNl5fe+epP7JI8Mk7hWSsT2RTyaGvWZzJBPqpK5j
-wa19hAM8EHiGG3njxPPyBJUgriOCxLM6AGK/5jYk4Ve6xx6QddVfP5VhK8E7zeWz
-aGHQRiapIVJpLesux+t3zqY6tQMzT3bR51xUAV3LePTJDL/PEo4XLSNolOer/qmy
-KwbQBM0=
------END CERTIFICATE-----

make/data/charsetmapping/GB18030.map

@@ -1,4 +1,6 @@
-# based on GB18030-2000 mapping
+# GB18030.java is NOT generated from this mapping right now. This
+# map is here for testing only.
+#
 00	0000
 01	0001
 02	0002

make/data/charsetmapping/charsets

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -477,11 +477,6 @@ charset x-IBM874 IBM874
     alias   ibm-874
     alias   874
 
-# alias for GB18030 is generated at runtime
-charset GB18030 GB18030
-    package sun.nio.cs
-    type    source
-
 ########################################################
 #
 # charsets provided by ExtendedCharsets provider.
@@ -569,6 +564,11 @@ charset GBK GBK                  # Simplified Chinese
     alias   windows-936
     alias   CP936
 
+charset GB18030 GB18030
+    package sun.nio.cs.ext
+    type    template
+    alias   gb18030-2000
+
 charset GB2312 EUC_CN
     package sun.nio.cs.ext
     type    dbcs

make/data/charsetmapping/stdcs-aix

@@ -7,6 +7,7 @@ Big5_HKSCS
 EUC_CN
 EUC_KR
 GBK
+GB18030
 IBM856
 IBM921
 IBM922

make/data/charsetmapping/stdcs-linux

@@ -11,6 +11,7 @@ EUC_JP_LINUX
 EUC_JP_Open
 EUC_TW
 GBK
+GB18030
 ISO_8859_11
 ISO_8859_3
 ISO_8859_6

make/data/charsetmapping/stdcs-solaris

@@ -0,0 +1,26 @@
+#
+#   generate these charsets into sun.nio.cs
+#
+Big5
+Big5_Solaris
+Big5_HKSCS        # always together with Big5
+EUC_CN
+EUC_KR
+EUC_JP
+EUC_JP_LINUX
+EUC_JP_Open
+EUC_TW
+GBK
+GB18030
+ISO_8859_11
+ISO_8859_3
+ISO_8859_6
+ISO_8859_8
+Johab
+PCK
+TIS_620
+JIS_X_0201
+JIS_X_0208
+JIS_X_0212
+JIS_X_0208_Solaris
+JIS_X_0212_Solaris

make/data/charsetmapping/stdcs-windows

@@ -2,6 +2,7 @@
 #   generate these charsets into sun.nio.cs
 #
 GBK
+GB18030
 Johab
 MS1255
 MS1256

make/data/currency/CurrencyData.properties

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -32,7 +32,7 @@ formatVersion=3
 # Version of the currency code information in this class.
 # It is a serial number that accompanies with each amendment.
 
-dataVersion=175
+dataVersion=174
 
 # List of all valid ISO 4217 currency codes.
 # To ensure compatibility, do not remove codes.

make/data/tzdata/VERSION

@@ -21,4 +21,4 @@
 # or visit www.oracle.com if you need additional information or have any
 # questions.
 #
-tzdata2023c
+tzdata2022g

make/data/tzdata/africa

@@ -344,14 +344,6 @@ Rule	Egypt	2007	only	-	Sep	Thu>=1	24:00	0	-
 # From Mina Samuel (2016-07-04):
 # Egyptian government took the decision to cancel the DST,
 
-# From Ahmad ElDardiry (2023-03-01):
-# Egypt officially announced today that daylight savings will be
-# applied from last Friday of April to last Thursday of October.
-# From Paul Eggert (2023-03-01):
-# Assume transitions are at 00:00 and 24:00 respectively.
-# From Amir Adib (2023-03-07):
-# https://www.facebook.com/EgyptianCabinet/posts/638829614954129/
-
 Rule	Egypt	2008	only	-	Aug	lastThu	24:00	0	-
 Rule	Egypt	2009	only	-	Aug	20	24:00	0	-
 Rule	Egypt	2010	only	-	Aug	10	24:00	0	-
@@ -361,8 +353,6 @@ Rule	Egypt	2014	only	-	May	15	24:00	1:00	S
 Rule	Egypt	2014	only	-	Jun	26	24:00	0	-
 Rule	Egypt	2014	only	-	Jul	31	24:00	1:00	S
 Rule	Egypt	2014	only	-	Sep	lastThu	24:00	0	-
-Rule	Egypt	2023	max	-	Apr	lastFri	 0:00	1:00	S
-Rule	Egypt	2023	max	-	Oct	lastThu	24:00	0	-
 
 # Zone	NAME		STDOFF	RULES	FORMAT	[UNTIL]
 		#STDOFF	2:05:08.9
@@ -462,7 +452,7 @@ Zone	Africa/Nairobi	2:27:16	-	LMT	1908 May
 # President William R. Tolbert, Jr., July 23, 1971-July 31, 1972.
 # Monrovia: Executive Mansion.
 #
-# Use the abbreviation "MMT" before 1972, as the more accurate numeric
+# Use the abbreviation "MMT" before 1972, as the more-accurate numeric
 # abbreviation "-004430" would be one byte over the POSIX limit.
 #
 # Zone	NAME		STDOFF	RULES	FORMAT	[UNTIL]
@@ -599,8 +589,8 @@ Zone	Africa/Tripoli	0:52:44 -	LMT	1920
 # DST the coming summer...
 #
 # Some sources, in French:
-# http://www.defimedia.info/news/946/Rashid-Beebeejaun-:-«-L%E2%80%99heure-d%E2%80%99été-ne-sera-pas-appliquée-cette-année-»
-# http://lexpress.mu/Story/3398~Beebeejaun---Les-objectifs-d-économie-d-énergie-de-l-heure-d-été-ont-été-atteints-
+# http://www.defimedia.info/news/946/Rashid-Beebeejaun-:-%C2%AB-L%E2%80%99heure-d%E2%80%99%C3%A9t%C3%A9-ne-sera-pas-appliqu%C3%A9e-cette-ann%C3%A9e-%C2%BB
+# http://lexpress.mu/Story/3398~Beebeejaun---Les-objectifs-d-%C3%A9conomie-d-%C3%A9nergie-de-l-heure-d-%C3%A9t%C3%A9-ont-%C3%A9t%C3%A9-atteints-
 #
 # Our wrap-up:
 # https://www.timeanddate.com/news/time/mauritius-dst-will-not-repeat.html
@@ -731,7 +721,7 @@ Zone Indian/Mauritius	3:50:00 -	LMT	1907 # Port Louis
 # More articles in the press
 # https://www.yabiladi.com/articles/details/5058/secret-l-heure-d-ete-maroc-leve.html
 # http://www.lematin.ma/Actualite/Express/Article.asp?id=148923
-# http://www.lavieeco.com/actualite/Le-Maroc-passe-sur-GMT+1-a-partir-de-dim
+# http://www.lavieeco.com/actualite/Le-Maroc-passe-sur-GMT%2B1-a-partir-de-dim
 
 # From Petr Machata (2011-03-30):
 # They have it written in English here:
@@ -746,7 +736,7 @@ Zone Indian/Mauritius	3:50:00 -	LMT	1907 # Port Louis
 # According to Infomédiaire web site from Morocco (infomediaire.ma),
 # on March 9, 2012, (in French) Heure légale:
 # Le Maroc adopte officiellement l'heure d'été
-# http://www.infomediaire.ma/news/maroc/heure-légale-le-maroc-adopte-officiellement-lheure-dété
+# http://www.infomediaire.ma/news/maroc/heure-l%C3%A9gale-le-maroc-adopte-officiellement-lheure-d%C3%A9t%C3%A9
 # Governing Council adopted draft decree, that Morocco DST starts on
 # the last Sunday of March (March 25, 2012) and ends on
 # last Sunday of September (September 30, 2012)
@@ -870,28 +860,19 @@ Zone Indian/Mauritius	3:50:00 -	LMT	1907 # Port Louis
 # Friday or Saturday (and so the 2 days off are on a weekend), the next time
 # shift will be the next weekend.
 #
-# From Milamber (2021-03-31, 2022-03-10):
-# https://www.mmsp.gov.ma/fr/actualites.aspx?id=2076
-# https://www.ecoactu.ma/horaires-administration-ramadan-gmtheure-gmt-a-partir-de-dimanche-27-mars/
-#
-# From Milamber (2023-03-14, 2023-03-15):
-# The return to legal GMT time will take place this Sunday, March 19 at 3 a.m.
-# ... the return to GMT+1 will be made on Sunday April 23, 2023 at 2 a.m.
-# https://www.mmsp.gov.ma/fr/actualites/passage-à-l%E2%80%99heure-gmt-à-partir-du-dimanche-19-mars-2023
-#
-# From Paul Eggert (2023-03-14):
+# From Paul Eggert (2020-05-31):
 # For now, guess that in the future Morocco will fall back at 03:00
 # the last Sunday before Ramadan, and spring forward at 02:00 the
-# first Sunday after one day after Ramadan.  To implement this,
+# first Sunday after two days after Ramadan.  To implement this,
 # transition dates and times for 2019 through 2087 were determined by
-# running the following program under GNU Emacs 28.2.  (This algorithm
+# running the following program under GNU Emacs 26.3.  (This algorithm
 # also produces the correct transition dates for 2016 through 2018,
 # though the times differ due to Morocco's time zone change in 2018.)
 # (let ((islamic-year 1440))
 #   (require 'cal-islam)
 #   (while (< islamic-year 1511)
 #     (let ((a (calendar-islamic-to-absolute (list 9 1 islamic-year)))
-#           (b (+ 1 (calendar-islamic-to-absolute (list 10 1 islamic-year))))
+#           (b (+ 2 (calendar-islamic-to-absolute (list 10 1 islamic-year))))
 #           (sunday 0))
 #       (while (/= sunday (mod (setq a (1- a)) 7)))
 #       (while (/= sunday (mod b 7))
@@ -905,6 +886,10 @@ Zone Indian/Mauritius	3:50:00 -	LMT	1907 # Port Louis
 #         (car (cdr (cdr a))) (calendar-month-name (car a) t) (car (cdr a))
 #         (car (cdr (cdr b))) (calendar-month-name (car b) t) (car (cdr b)))))
 #     (setq islamic-year (+ 1 islamic-year))))
+#
+# From Milamber (2021-03-31, 2022-03-10), confirming these predictions:
+# https://www.mmsp.gov.ma/fr/actualites.aspx?id=2076
+# https://www.ecoactu.ma/horaires-administration-ramadan-gmtheure-gmt-a-partir-de-dimanche-27-mars/
 
 # Rule	NAME	FROM	TO	-	IN	ON	AT	SAVE	LETTER/S
 Rule	Morocco	1939	only	-	Sep	12	 0:00	1:00	-
@@ -957,7 +942,7 @@ Rule	Morocco	2021	only	-	May	16	 2:00	0	-
 Rule	Morocco	2022	only	-	Mar	27	 3:00	-1:00	-
 Rule	Morocco	2022	only	-	May	 8	 2:00	0	-
 Rule	Morocco	2023	only	-	Mar	19	 3:00	-1:00	-
-Rule	Morocco	2023	only	-	Apr	23	 2:00	0	-
+Rule	Morocco	2023	only	-	Apr	30	 2:00	0	-
 Rule	Morocco	2024	only	-	Mar	10	 3:00	-1:00	-
 Rule	Morocco	2024	only	-	Apr	14	 2:00	0	-
 Rule	Morocco	2025	only	-	Feb	23	 3:00	-1:00	-
@@ -973,7 +958,7 @@ Rule	Morocco	2029	only	-	Feb	18	 2:00	0	-
 Rule	Morocco	2029	only	-	Dec	30	 3:00	-1:00	-
 Rule	Morocco	2030	only	-	Feb	10	 2:00	0	-
 Rule	Morocco	2030	only	-	Dec	22	 3:00	-1:00	-
-Rule	Morocco	2031	only	-	Jan	26	 2:00	0	-
+Rule	Morocco	2031	only	-	Feb	 2	 2:00	0	-
 Rule	Morocco	2031	only	-	Dec	14	 3:00	-1:00	-
 Rule	Morocco	2032	only	-	Jan	18	 2:00	0	-
 Rule	Morocco	2032	only	-	Nov	28	 3:00	-1:00	-
@@ -989,7 +974,7 @@ Rule	Morocco	2036	only	-	Nov	23	 2:00	0	-
 Rule	Morocco	2037	only	-	Oct	 4	 3:00	-1:00	-
 Rule	Morocco	2037	only	-	Nov	15	 2:00	0	-
 Rule	Morocco	2038	only	-	Sep	26	 3:00	-1:00	-
-Rule	Morocco	2038	only	-	Oct	31	 2:00	0	-
+Rule	Morocco	2038	only	-	Nov	 7	 2:00	0	-
 Rule	Morocco	2039	only	-	Sep	18	 3:00	-1:00	-
 Rule	Morocco	2039	only	-	Oct	23	 2:00	0	-
 Rule	Morocco	2040	only	-	Sep	 2	 3:00	-1:00	-
@@ -1005,7 +990,7 @@ Rule	Morocco	2044	only	-	Aug	28	 2:00	0	-
 Rule	Morocco	2045	only	-	Jul	 9	 3:00	-1:00	-
 Rule	Morocco	2045	only	-	Aug	20	 2:00	0	-
 Rule	Morocco	2046	only	-	Jul	 1	 3:00	-1:00	-
-Rule	Morocco	2046	only	-	Aug	 5	 2:00	0	-
+Rule	Morocco	2046	only	-	Aug	12	 2:00	0	-
 Rule	Morocco	2047	only	-	Jun	23	 3:00	-1:00	-
 Rule	Morocco	2047	only	-	Jul	28	 2:00	0	-
 Rule	Morocco	2048	only	-	Jun	 7	 3:00	-1:00	-
@@ -1021,7 +1006,7 @@ Rule	Morocco	2052	only	-	Jun	 2	 2:00	0	-
 Rule	Morocco	2053	only	-	Apr	13	 3:00	-1:00	-
 Rule	Morocco	2053	only	-	May	25	 2:00	0	-
 Rule	Morocco	2054	only	-	Apr	 5	 3:00	-1:00	-
-Rule	Morocco	2054	only	-	May	10	 2:00	0	-
+Rule	Morocco	2054	only	-	May	17	 2:00	0	-
 Rule	Morocco	2055	only	-	Mar	28	 3:00	-1:00	-
 Rule	Morocco	2055	only	-	May	 2	 2:00	0	-
 Rule	Morocco	2056	only	-	Mar	12	 3:00	-1:00	-
@@ -1037,7 +1022,7 @@ Rule	Morocco	2060	only	-	Mar	 7	 2:00	0	-
 Rule	Morocco	2061	only	-	Jan	16	 3:00	-1:00	-
 Rule	Morocco	2061	only	-	Feb	27	 2:00	0	-
 Rule	Morocco	2062	only	-	Jan	 8	 3:00	-1:00	-
-Rule	Morocco	2062	only	-	Feb	12	 2:00	0	-
+Rule	Morocco	2062	only	-	Feb	19	 2:00	0	-
 Rule	Morocco	2062	only	-	Dec	31	 3:00	-1:00	-
 Rule	Morocco	2063	only	-	Feb	 4	 2:00	0	-
 Rule	Morocco	2063	only	-	Dec	16	 3:00	-1:00	-
@@ -1053,7 +1038,7 @@ Rule	Morocco	2067	only	-	Dec	11	 2:00	0	-
 Rule	Morocco	2068	only	-	Oct	21	 3:00	-1:00	-
 Rule	Morocco	2068	only	-	Dec	 2	 2:00	0	-
 Rule	Morocco	2069	only	-	Oct	13	 3:00	-1:00	-
-Rule	Morocco	2069	only	-	Nov	17	 2:00	0	-
+Rule	Morocco	2069	only	-	Nov	24	 2:00	0	-
 Rule	Morocco	2070	only	-	Oct	 5	 3:00	-1:00	-
 Rule	Morocco	2070	only	-	Nov	 9	 2:00	0	-
 Rule	Morocco	2071	only	-	Sep	20	 3:00	-1:00	-
@@ -1069,7 +1054,7 @@ Rule	Morocco	2075	only	-	Sep	15	 2:00	0	-
 Rule	Morocco	2076	only	-	Jul	26	 3:00	-1:00	-
 Rule	Morocco	2076	only	-	Sep	 6	 2:00	0	-
 Rule	Morocco	2077	only	-	Jul	18	 3:00	-1:00	-
-Rule	Morocco	2077	only	-	Aug	22	 2:00	0	-
+Rule	Morocco	2077	only	-	Aug	29	 2:00	0	-
 Rule	Morocco	2078	only	-	Jul	10	 3:00	-1:00	-
 Rule	Morocco	2078	only	-	Aug	14	 2:00	0	-
 Rule	Morocco	2079	only	-	Jun	25	 3:00	-1:00	-
@@ -1079,13 +1064,13 @@ Rule	Morocco	2080	only	-	Jul	21	 2:00	0	-
 Rule	Morocco	2081	only	-	Jun	 1	 3:00	-1:00	-
 Rule	Morocco	2081	only	-	Jul	13	 2:00	0	-
 Rule	Morocco	2082	only	-	May	24	 3:00	-1:00	-
-Rule	Morocco	2082	only	-	Jun	28	 2:00	0	-
+Rule	Morocco	2082	only	-	Jul	 5	 2:00	0	-
 Rule	Morocco	2083	only	-	May	16	 3:00	-1:00	-
 Rule	Morocco	2083	only	-	Jun	20	 2:00	0	-
 Rule	Morocco	2084	only	-	Apr	30	 3:00	-1:00	-
 Rule	Morocco	2084	only	-	Jun	11	 2:00	0	-
 Rule	Morocco	2085	only	-	Apr	22	 3:00	-1:00	-
-Rule	Morocco	2085	only	-	May	27	 2:00	0	-
+Rule	Morocco	2085	only	-	Jun	 3	 2:00	0	-
 Rule	Morocco	2086	only	-	Apr	14	 3:00	-1:00	-
 Rule	Morocco	2086	only	-	May	19	 2:00	0	-
 Rule	Morocco	2087	only	-	Mar	30	 3:00	-1:00	-
@@ -1228,15 +1213,15 @@ Zone	Africa/Windhoek	1:08:24 -	LMT	1892 Feb 8
 # From P Chan (2020-12-03):
 # GMT was adopted as the standard time of Lagos on 1905-07-01.
 # Lagos Weekly Record, 1905-06-24, p 3
-# http://ddsnext.crl.edu/titles/31558#?c=0&m=668&s=0&cv=2&r=0&xywh=1446,5221,1931,1235
+# http://ddsnext.crl.edu/titles/31558#?c=0&m=668&s=0&cv=2&r=0&xywh=1446%2C5221%2C1931%2C1235
 # says "It is officially notified that on and after the 1st of July 1905
-# Greenwich Mean Solar Time will be adopted throughout the Colony and
+# Greenwich Mean Solar Time will be adopted thought the Colony and
 # Protectorate, and that it will be necessary to put all clocks 13 minutes and
 # 35 seconds back, recording local mean time."
 #
 # It seemed that Lagos returned to LMT on 1908-07-01.
 # [The Lagos Standard], 1908-07-01, p 5
-# http://ddsnext.crl.edu/titles/31556#?c=0&m=78&s=0&cv=4&r=0&xywh=-92,3590,3944,2523
+# http://ddsnext.crl.edu/titles/31556#?c=0&m=78&s=0&cv=4&r=0&xywh=-92%2C3590%2C3944%2C2523
 # says "Scarcely have the people become accustomed to this new time, when
 # another official notice has now appeared announcing that from and after the
 # 1st July next, return will be made to local mean time."
@@ -1248,7 +1233,7 @@ Zone	Africa/Windhoek	1:08:24 -	LMT	1892 Feb 8
 # https://libsysdigi.library.illinois.edu/ilharvest/Africana/Books2011-05/3064634/3064634_1914/3064634_1914_opt.pdf#page=27
 # "On January 1st [1914], a universal standard time for Nigeria was adopted,
 # viz., half an hour fast on Greenwich mean time, corresponding to the meridian
-# 7° 30' E. long."
+# 7 [degrees] 30' E. long."
 # Lloyd's Register of Shipping (1915) says "Hitherto the time observed in Lagos
 # was the local mean time. On 1st January, 1914, standard time for the whole of
 # Nigeria was introduced ... Lagos time has been advanced about 16 minutes
@@ -1266,7 +1251,7 @@ Zone	Africa/Windhoek	1:08:24 -	LMT	1892 Feb 8
 # The Lagos Weekly Record, 1919-09-20, p 3 details discussion on the first
 # reading of this Bill by the Legislative Council of the Colony of Nigeria on
 # Thursday 1919-08-28:
-# http://ddsnext.crl.edu/titles/31558?terms&item_id=303484#?m=1118&c=1&s=0&cv=2&r=0&xywh=1261,3408,2994,1915
+# http://ddsnext.crl.edu/titles/31558?terms&item_id=303484#?m=1118&c=1&s=0&cv=2&r=0&xywh=1261%2C3408%2C2994%2C1915
 # "The proposal is that the Globe should be divided into twelve zones East and
 # West of Greenwich, of one hour each, Nigeria falling into the zone with a
 # standard of one hour fast on Greenwich Mean Time.  Nigeria standard time is

make/data/tzdata/antarctica

@@ -315,7 +315,7 @@ Zone Antarctica/Rothera	0	-	-00	1976 Dec  1
 # but that he found it more convenient to keep GMT+12
 # as supplies for the station were coming from McMurdo Sound,
 # which was on GMT+12 because New Zealand was on GMT+12 all year
-# at that time (1957).  (Source: Siple's book 90° South.)
+# at that time (1957).  (Source: Siple's book 90 Degrees South.)
 #
 # From Susan Smith
 # http://www.cybertours.com/whs/pole10.html

make/data/tzdata/asia

@@ -2714,40 +2714,6 @@ Zone	Asia/Pyongyang	8:23:00 -	LMT	1908 Apr  1
 
 
 # Lebanon
-#
-# From Saadallah Itani (2023-03-23):
-# Lebanon ... announced today delay of Spring forward from March 25 to April 20.
-#
-# From Paul Eggert (2023-03-27):
-# This announcement was by the Lebanese caretaker prime minister Najib Mikati.
-# https://www.mtv.com.lb/en/News/Local/1352516/lebanon-postpones-daylight-saving-time-adoption
-# A video was later leaked to the media of parliament speaker Nabih Berri
-# asking Mikati to postpone DST to aid observance of Ramadan, Mikati objecting
-# that this would cause problems such as scheduling airline flights, to which
-# Berri interjected, "What flights?"
-#
-# The change was controversial and led to a partly-sectarian divide.
-# Many Lebanese institutions, including the education ministry, the Maronite
-# church, and two news channels LCBI and MTV, ignored the announcement and
-# went ahead with the long-scheduled spring-forward on March 25/26, some
-# arguing that the prime minister had not followed the law because the change
-# had not been approved by the cabinet.  Google went with the announcement;
-# Apple ignored it.  At least one bank followed the announcement for its doors,
-# but ignored the announcement in internal computer systems.
-# Beirut international airport listed two times for each departure.
-# Dan Azzi wrote "My view is that this whole thing is a Dumb and Dumber movie."
-# Eventually the prime minister backed down, said the cabinet had decided to
-# stick with its 1998 decision, and that DST would begin midnight March 29/30.
-# https://www.nna-leb.gov.lb/en/miscellaneous/604093/lebanon-has-two-times-of-day-amid-daylight-savings
-# https://www.cnbc.com/2023/03/27/lebanon-in-two-different-time-zones-as-government-disagrees-on-daylight-savings.html
-#
-# Although we could model the chaos with two Zones, that would likely cause
-# more trouble than it would cure.  Since so many manual clocks and
-# computer-based timestamps ignored the announcement, stick with official
-# cabinet resolutions in the data while recording the prime minister's
-# announcement as a comment.  This is how we treated a similar situation in
-# Rio de Janeiro in spring 1993.
-#
 # Rule	NAME	FROM	TO	-	IN	ON	AT	SAVE	LETTER/S
 Rule	Lebanon	1920	only	-	Mar	28	0:00	1:00	S
 Rule	Lebanon	1920	only	-	Oct	25	0:00	0	-
@@ -2773,10 +2739,6 @@ Rule	Lebanon	1992	only	-	Oct	4	0:00	0	-
 Rule	Lebanon	1993	max	-	Mar	lastSun	0:00	1:00	S
 Rule	Lebanon	1993	1998	-	Sep	lastSun	0:00	0	-
 Rule	Lebanon	1999	max	-	Oct	lastSun	0:00	0	-
-# This one-time rule, announced by the prime minister first for April 21
-# then for March 30, is commented out for reasons described above.
-#Rule	Lebanon	2023	only	-	Mar	30	0:00	1:00	S
-
 # Zone	NAME		STDOFF	RULES	FORMAT	[UNTIL]
 Zone	Asia/Beirut	2:22:00 -	LMT	1880
 			2:00	Lebanon	EE%sT
@@ -3015,7 +2977,7 @@ Zone	Asia/Kathmandu	5:41:16 -	LMT	1920
 # 9pm and moving clocks forward by one hour for the next three months. ...."
 #
 # http://www.worldtimezone.com/dst_news/dst_news_pakistan01.html
-# http://www.dailytimes.com.pk/default.asp?page=2008\05\15\story_15-5-2008_pg1_4
+# http://www.dailytimes.com.pk/default.asp?page=2008%5C05%5C15%5Cstory_15-5-2008_pg1_4
 
 # From Arthur David Olson (2008-05-19):
 # XXX--midnight transitions is a guess; 2008 only is a guess.
@@ -3338,7 +3300,7 @@ Zone	Asia/Karachi	4:28:12 -	LMT	1907
 # Some of many sources in Arabic:
 # http://www.samanews.com/index.php?act=Show&id=122638
 #
-# http://safa.ps/details/news/74352/بدء-التوقيت-الصيفي-بالضفة-وغزة-ليلة-الجمعة.html
+# http://safa.ps/details/news/74352/%D8%A8%D8%AF%D8%A1-%D8%A7%D9%84%D8%AA%D9%88%D9%82%D9%8A%D8%AA-%D8%A7%D9%84%D8%B5%D9%8A%D9%81%D9%8A-%D8%A8%D8%A7%D9%84%D8%B6%D9%81%D8%A9-%D9%88%D8%BA%D8%B2%D8%A9-%D9%84%D9%8A%D9%84%D8%A9-%D8%A7%D9%84%D8%AC%D9%85%D8%B9%D8%A9.html
 #
 # Our brief summary:
 # https://www.timeanddate.com/news/time/gaza-west-bank-dst-2012.html
@@ -3348,7 +3310,7 @@ Zone	Asia/Karachi	4:28:12 -	LMT	1907
 # time from midnight on Friday, March 29, 2013" (translated).
 # [These are in Arabic and are for Gaza and for Ramallah, respectively.]
 # http://www.samanews.com/index.php?act=Show&id=154120
-# http://safa.ps/details/news/99844/رام-الله-بدء-التوقيت-الصيفي-29-الجاري.html
+# http://safa.ps/details/news/99844/%D8%B1%D8%A7%D9%85-%D8%A7%D9%84%D9%84%D9%87-%D8%A8%D8%AF%D8%A1-%D8%A7%D9%84%D8%AA%D9%88%D9%82%D9%8A%D8%AA-%D8%A7%D9%84%D8%B5%D9%8A%D9%81%D9%8A-29-%D8%A7%D9%84%D8%AC%D8%A7%D8%B1%D9%8A.html
 
 # From Steffen Thorsen (2013-09-24):
 # The Gaza and West Bank are ending DST Thursday at midnight
@@ -3446,41 +3408,9 @@ Zone	Asia/Karachi	4:28:12 -	LMT	1907
 # (2022-08-31): ... the Saturday before the last Sunday in March and October
 # at 2:00 AM ,for the years from 2023 to 2026.
 # (2022-09-05): https://mtit.pna.ps/Site/New/1453
-
-# From Heba Hamad (2023-03-22):
-# ... summer time will begin in Palestine from Saturday 04-29-2023,
-# 02:00 AM by 60 minutes forward.
 #
-# From Paul Eggert (2023-03-22):
-# For now, guess that spring and fall transitions will normally
-# continue to use 2022's rules, that during DST Palestine will switch
-# to standard time at 02:00 the last Saturday before Ramadan and back
-# to DST at 02:00 the first Saturday after Ramadan, and that
-# if the normal spring-forward or fall-back transition occurs during
-# Ramadan the former is delayed and the latter advanced.
-# To implement this, I predicted Ramadan-oriented transition dates for
-# 2023 through 2086 by running the following program under GNU Emacs 28.2,
-# with the results integrated by hand into the table below.
-# Predictions after 2086 are approximated without Ramadan.
-#
-# (let ((islamic-year 1444))
-#   (require 'cal-islam)
-#   (while (< islamic-year 1510)
-#     (let ((a (calendar-islamic-to-absolute (list 9 1 islamic-year)))
-#           (b (+ 1 (calendar-islamic-to-absolute (list 10 1 islamic-year))))
-#           (saturday 6))
-#       (while (/= saturday (mod (setq a (1- a)) 7)))
-#       (while (/= saturday (mod b 7))
-#         (setq b (1+ b)))
-#       (setq a (calendar-gregorian-from-absolute a))
-#       (setq b (calendar-gregorian-from-absolute b))
-#       (insert
-#        (format
-#         (concat "Rule Palestine\t%d\tonly\t-\t%s\t%2d\t2:00\t0\t-\n"
-#                 "Rule Palestine\t%d\tonly\t-\t%s\t%2d\t2:00\t1:00\tS\n")
-#         (car (cdr (cdr a))) (calendar-month-name (car a) t) (car (cdr a))
-#         (car (cdr (cdr b))) (calendar-month-name (car b) t) (car (cdr b)))))
-#     (setq islamic-year (+ 1 islamic-year))))
+# From Paul Eggert (2022-08-31):
+# For now, assume that this rule will also be used after 2026.
 
 # Rule	NAME	FROM	TO	-	IN	ON	AT	SAVE	LETTER/S
 Rule EgyptAsia	1957	only	-	May	10	0:00	1:00	S
@@ -3520,86 +3450,8 @@ Rule Palestine	2020	2021	-	Mar	Sat<=30	0:00	1:00	S
 Rule Palestine	2020	only	-	Oct	24	1:00	0	-
 Rule Palestine	2021	only	-	Oct	29	1:00	0	-
 Rule Palestine	2022	only	-	Mar	27	0:00	1:00	S
-Rule Palestine	2022	2035	-	Oct	Sat<=30	2:00	0	-
-Rule Palestine	2023	only	-	Apr	29	2:00	1:00	S
-Rule Palestine	2024	only	-	Apr	13	2:00	1:00	S
-Rule Palestine	2025	only	-	Apr	 5	2:00	1:00	S
-Rule Palestine	2026	2054	-	Mar	Sat<=30	2:00	1:00	S
-Rule Palestine	2036	only	-	Oct	18	2:00	0	-
-Rule Palestine	2037	only	-	Oct	10	2:00	0	-
-Rule Palestine	2038	only	-	Sep	25	2:00	0	-
-Rule Palestine	2039	only	-	Sep	17	2:00	0	-
-Rule Palestine	2039	only	-	Oct	22	2:00	1:00	S
-Rule Palestine	2039	2067	-	Oct	Sat<=30	2:00	0	-
-Rule Palestine	2040	only	-	Sep	 1	2:00	0	-
-Rule Palestine	2040	only	-	Oct	13	2:00	1:00	S
-Rule Palestine	2041	only	-	Aug	24	2:00	0	-
-Rule Palestine	2041	only	-	Sep	28	2:00	1:00	S
-Rule Palestine	2042	only	-	Aug	16	2:00	0	-
-Rule Palestine	2042	only	-	Sep	20	2:00	1:00	S
-Rule Palestine	2043	only	-	Aug	 1	2:00	0	-
-Rule Palestine	2043	only	-	Sep	12	2:00	1:00	S
-Rule Palestine	2044	only	-	Jul	23	2:00	0	-
-Rule Palestine	2044	only	-	Aug	27	2:00	1:00	S
-Rule Palestine	2045	only	-	Jul	15	2:00	0	-
-Rule Palestine	2045	only	-	Aug	19	2:00	1:00	S
-Rule Palestine	2046	only	-	Jun	30	2:00	0	-
-Rule Palestine	2046	only	-	Aug	11	2:00	1:00	S
-Rule Palestine	2047	only	-	Jun	22	2:00	0	-
-Rule Palestine	2047	only	-	Jul	27	2:00	1:00	S
-Rule Palestine	2048	only	-	Jun	 6	2:00	0	-
-Rule Palestine	2048	only	-	Jul	18	2:00	1:00	S
-Rule Palestine	2049	only	-	May	29	2:00	0	-
-Rule Palestine	2049	only	-	Jul	 3	2:00	1:00	S
-Rule Palestine	2050	only	-	May	21	2:00	0	-
-Rule Palestine	2050	only	-	Jun	25	2:00	1:00	S
-Rule Palestine	2051	only	-	May	 6	2:00	0	-
-Rule Palestine	2051	only	-	Jun	17	2:00	1:00	S
-Rule Palestine	2052	only	-	Apr	27	2:00	0	-
-Rule Palestine	2052	only	-	Jun	 1	2:00	1:00	S
-Rule Palestine	2053	only	-	Apr	12	2:00	0	-
-Rule Palestine	2053	only	-	May	24	2:00	1:00	S
-Rule Palestine	2054	only	-	Apr	 4	2:00	0	-
-Rule Palestine	2054	only	-	May	16	2:00	1:00	S
-Rule Palestine	2055	only	-	May	 1	2:00	1:00	S
-Rule Palestine	2056	only	-	Apr	22	2:00	1:00	S
-Rule Palestine	2057	only	-	Apr	 7	2:00	1:00	S
-Rule Palestine	2058	max	-	Mar	Sat<=30	2:00	1:00	S
-Rule Palestine	2068	only	-	Oct	20	2:00	0	-
-Rule Palestine	2069	only	-	Oct	12	2:00	0	-
-Rule Palestine	2070	only	-	Oct	 4	2:00	0	-
-Rule Palestine	2071	only	-	Sep	19	2:00	0	-
-Rule Palestine	2072	only	-	Sep	10	2:00	0	-
-Rule Palestine	2072	only	-	Oct	15	2:00	1:00	S
-Rule Palestine	2073	only	-	Sep	 2	2:00	0	-
-Rule Palestine	2073	only	-	Oct	 7	2:00	1:00	S
-Rule Palestine	2074	only	-	Aug	18	2:00	0	-
-Rule Palestine	2074	only	-	Sep	29	2:00	1:00	S
-Rule Palestine	2075	only	-	Aug	10	2:00	0	-
-Rule Palestine	2075	only	-	Sep	14	2:00	1:00	S
-Rule Palestine	2075	max	-	Oct	Sat<=30	2:00	0	-
-Rule Palestine	2076	only	-	Jul	25	2:00	0	-
-Rule Palestine	2076	only	-	Sep	 5	2:00	1:00	S
-Rule Palestine	2077	only	-	Jul	17	2:00	0	-
-Rule Palestine	2077	only	-	Aug	28	2:00	1:00	S
-Rule Palestine	2078	only	-	Jul	 9	2:00	0	-
-Rule Palestine	2078	only	-	Aug	13	2:00	1:00	S
-Rule Palestine	2079	only	-	Jun	24	2:00	0	-
-Rule Palestine	2079	only	-	Aug	 5	2:00	1:00	S
-Rule Palestine	2080	only	-	Jun	15	2:00	0	-
-Rule Palestine	2080	only	-	Jul	20	2:00	1:00	S
-Rule Palestine	2081	only	-	Jun	 7	2:00	0	-
-Rule Palestine	2081	only	-	Jul	12	2:00	1:00	S
-Rule Palestine	2082	only	-	May	23	2:00	0	-
-Rule Palestine	2082	only	-	Jul	 4	2:00	1:00	S
-Rule Palestine	2083	only	-	May	15	2:00	0	-
-Rule Palestine	2083	only	-	Jun	19	2:00	1:00	S
-Rule Palestine	2084	only	-	Apr	29	2:00	0	-
-Rule Palestine	2084	only	-	Jun	10	2:00	1:00	S
-Rule Palestine	2085	only	-	Apr	21	2:00	0	-
-Rule Palestine	2085	only	-	Jun	 2	2:00	1:00	S
-Rule Palestine	2086	only	-	Apr	13	2:00	0	-
-Rule Palestine	2086	only	-	May	18	2:00	1:00	S
+Rule Palestine	2022	max	-	Oct	Sat<=30	2:00	0	-
+Rule Palestine	2023	max	-	Mar	Sat<=30	2:00	1:00	S
 
 # Zone	NAME		STDOFF	RULES	FORMAT	[UNTIL]
 Zone	Asia/Gaza	2:17:52	-	LMT	1900 Oct
@@ -3803,7 +3655,7 @@ Zone	Asia/Singapore	6:55:25 -	LMT	1901 Jan  1
 # standard time is SLST.
 #
 # From Paul Eggert (2016-10-18):
-# "SLST" seems to be reasonably recent and rarely used outside time
+# "SLST" seems to be reasonably recent and rarely-used outside time
 # zone nerd sources.  I searched Google News and found three uses of
 # it in the International Business Times of India in February and
 # March of this year when discussing cricket match times, but nothing

make/data/tzdata/australasia

@@ -346,7 +346,7 @@ Zone Antarctica/Macquarie 0	-	-00	1899 Nov
 
 # From Steffen Thorsen (2013-01-10):
 # Fiji will end DST on 2014-01-19 02:00:
-# http://www.fiji.gov.fj/Media-Center/Press-Releases/DAYLIGHT-SAVINGS-TO-END-THIS-MONTH-(1).aspx
+# http://www.fiji.gov.fj/Media-Center/Press-Releases/DAYLIGHT-SAVINGS-TO-END-THIS-MONTH-%281%29.aspx
 
 # From Ken Rylander (2014-10-20):
 # DST will start Nov. 2 this year.
@@ -746,7 +746,7 @@ Zone Pacific/Pago_Pago	 12:37:12 -	LMT	1892 Jul  5
 #
 # Samoa's Daylight Saving Time Act 2009 is available here, but does not
 # contain any dates:
-# http://www.parliament.gov.ws/documents/acts/Daylight%20Saving%20Act%20%202009%20(English)%20-%20Final%207-7-091.pdf
+# http://www.parliament.gov.ws/documents/acts/Daylight%20Saving%20Act%20%202009%20%28English%29%20-%20Final%207-7-091.pdf
 
 # From Laupue Raymond Hughes (2010-10-07):
 # Please see
@@ -1831,7 +1831,7 @@ Zone	Pacific/Efate	11:13:16 -	LMT	1912 Jan 13 # Vila
 # period.  It would probably be reasonable to assume Guam use GMT+9 during
 # that period of time like the surrounding area.
 
-# From Paul Eggert (2023-01-23):
+# From Paul Eggert (2018-11-18):
 # Howse writes (p 153) "The Spaniards, on the other hand, reached the
 # Philippines and the Ladrones from America," and implies that the Ladrones
 # (now called the Marianas) kept American date for quite some time.
@@ -1844,7 +1844,7 @@ Zone	Pacific/Efate	11:13:16 -	LMT	1912 Jan 13 # Vila
 # they did as that avoids the need for a separate zone due to our 1970 cutoff.
 #
 # US Public Law 106-564 (2000-12-23) made UT +10 the official standard time,
-# under the name "Chamorro standard time".  There is no official abbreviation,
+# under the name "Chamorro Standard Time".  There is no official abbreviation,
 # but Congressman Robert A. Underwood, author of the bill that became law,
 # wrote in a press release (2000-12-27) that he will seek the use of "ChST".
 
@@ -2222,18 +2222,24 @@ Zone	Pacific/Efate	11:13:16 -	LMT	1912 Jan 13 # Vila
 # an international standard, there are some places on the high seas where the
 # correct date is ambiguous.
 
-# From Wikipedia <https://en.wikipedia.org/wiki/Nautical_time> (2023-01-23):
-# The nautical time zone system is analogous to the terrestrial time zone
-# system for use on high seas.  Under the system time changes are required for
-# changes of longitude in one-hour steps.  The one-hour step corresponds to a
-# time zone width of 15° longitude.  The 15° gore that is offset from GMT or
-# UT1 (not UTC) by twelve hours is bisected by the nautical date line into two
-# 7°30' gores that differ from GMT by ±12 hours.  A nautical date line is
-# implied but not explicitly drawn on time zone maps.  It follows the 180th
-# meridian except where it is interrupted by territorial waters adjacent to
-# land, forming gaps: it is a pole-to-pole dashed line.
+# From Wikipedia <https://en.wikipedia.org/wiki/Time_zone> (2005-08-31):
+# Before 1920, all ships kept local apparent time on the high seas by setting
+# their clocks at night or at the morning sight so that, given the ship's
+# speed and direction, it would be 12 o'clock when the Sun crossed the ship's
+# meridian (12 o'clock = local apparent noon).  During 1917, at the
+# Anglo-French Conference on Time-keeping at Sea, it was recommended that all
+# ships, both military and civilian, should adopt hourly standard time zones
+# on the high seas.  Whenever a ship was within the territorial waters of any
+# nation it would use that nation's standard time.  The captain was permitted
+# to change his ship's clocks at a time of his choice following his ship's
+# entry into another zone time - he often chose midnight.  These zones were
+# adopted by all major fleets between 1920 and 1925 but not by many
+# independent merchant ships until World War II.
 
-# From Paul Eggert (2023-01-23):
-# The American Practical Navigator <https://msi.nga.mil/Publications/APN>,
-# 2019 edition, merely says that the International Date Line
-# "coincides with the 180th meridian over most of its length."
+# From Paul Eggert, using references suggested by Oscar van Vlijmen
+# (2005-03-20):
+#
+# The American Practical Navigator (2002)
+# http://pollux.nss.nima.mil/pubs/pubs_j_apn_sections.html?rid=187
+# talks only about the 180-degree meridian with respect to ships in
+# international waters; it ignores the international date line.

make/data/tzdata/backward

@@ -297,7 +297,6 @@ Link	America/Argentina/Cordoba	America/Rosario
 Link	America/Tijuana		America/Santa_Isabel
 Link	America/Denver		America/Shiprock
 Link	America/Toronto		America/Thunder_Bay
-Link	America/Edmonton	America/Yellowknife
 Link	Pacific/Auckland	Antarctica/South_Pole
 Link	Asia/Shanghai		Asia/Chongqing
 Link	Asia/Shanghai		Asia/Harbin

make/data/tzdata/europe

@@ -540,7 +540,9 @@ Zone	Europe/London	-0:01:15 -	LMT	1847 Dec  1
 # other form with a traditional approximation for Irish timestamps
 # after 1971-10-31 02:00 UTC; although this approximation has tm_isdst
 # flags that are reversed, its UTC offsets are correct and this often
-# suffices....
+# suffices.  This source file currently uses only nonnegative SAVE
+# values, but this is intended to change and downstream code should
+# not rely on it.
 #
 # The following is like GB-Eire and EU, except with standard time in
 # summer and negative daylight saving time in winter.  It is for when
@@ -1134,18 +1136,19 @@ Zone Atlantic/Faroe	-0:27:04 -	LMT	1908 Jan 11 # Tórshavn
 #
 # From Jürgen Appel (2022-11-25):
 # https://ina.gl/samlinger/oversigt-over-samlinger/samling/dagsordener/dagsorden.aspx?lang=da&day=24-11-2022
+# If I understand this correctly, from the next planned switch to
+# summer time, Greenland will permanently stay at that time, i.e. no
+# switch back to winter time in 2023 will occur.
 #
-# From Thomas M. Steenholdt (2022-12-02):
-# - The bill to move America/Nuuk from UTC-03 to UTC-02 passed.
-# - The bill to stop observing DST did not (Greenland will stop observing DST
-#   when EU does).
-# Details on the implementation are here (section 6):
-# https://ina.gl/dvd/EM%202022/pdf/media/2553529/pkt17_em2022_tidens_bestemmelse_bem_da.pdf
-# This is how the change will be implemented:
-# 1. The shift *to* DST in 2023 happens as normal.
-# 2. The shift *from* DST in 2023 happens as normal, but coincides with the
-#    shift to UTC-02 normaltime (people will not change their clocks here).
-# 3. After this, DST is still observed, but as -02/-01 instead of -03/-02.
+# From Paul Eggert (2022-11-28):
+# The official document in Danish
+# https://naalakkersuisut.gl/-/media/naalakkersuisut/filer/kundgoerelser/2022/11/2511/31_da_inatsisartutlov-om-tidens-bestemmelse.pdf?la=da&hash=A33597D8A38CC7038465241119EF34F3
+# says standard time for Greenland is -02, that Naalakkersuisut can lay down
+# rules for DST and can require some areas to use a different time zone,
+# and that this all takes effect 2023-03-25 22:00.  The abovementioned
+# "bekymringer" URL says the intent is no transition March 25, that
+# Greenland will not go back to winter time in fall 2023, and that
+# only America/Nuuk is affected (though further changes may occur).
 
 # Rule	NAME	FROM	TO	-	IN	ON	AT	SAVE	LETTER/S
 Rule	Thule	1991	1992	-	Mar	lastSun	2:00	1:00	D
@@ -1169,8 +1172,8 @@ Zone America/Scoresbysund -1:27:52 -	LMT	1916 Jul 28 # Ittoqqortoormiit
 			-1:00	EU	-01/+00
 Zone America/Nuuk	-3:26:56 -	LMT	1916 Jul 28 # Godthåb
 			-3:00	-	-03	1980 Apr  6  2:00
-			-3:00	EU	-03/-02	2023 Oct 29  1:00u
-			-2:00	EU	-02/-01
+			-3:00	EU	-03/-02	2023 Mar 25 22:00
+			-2:00	-	-02
 Zone America/Thule	-4:35:08 -	LMT	1916 Jul 28 # Pituffik
 			-4:00	Thule	A%sT
 
@@ -1506,9 +1509,9 @@ Zone	Europe/Paris	0:09:21 -	LMT	1891 Mar 16
 Rule	Germany	1946	only	-	Apr	14	2:00s	1:00	S
 Rule	Germany	1946	only	-	Oct	 7	2:00s	0	-
 Rule	Germany	1947	1949	-	Oct	Sun>=1	2:00s	0	-
-# https://www.ptb.de/cms/en/ptb/fachabteilungen/abt4/fb-44/ag-441/realisation-of-legal-time-in-germany/dst-and-midsummer-dst-in-germany-until-1979.html
-# says the following transition occurred at 3:00 MEZ, not the 2:00 MEZ
-# given in Shanks & Pottenger. Go with the PTB.
+# http://www.ptb.de/de/org/4/44/441/salt.htm says the following transition
+# occurred at 3:00 MEZ, not the 2:00 MEZ given in Shanks & Pottenger.
+# Go with the PTB.
 Rule	Germany	1947	only	-	Apr	 6	3:00s	1:00	S
 Rule	Germany	1947	only	-	May	11	2:00s	2:00	M
 Rule	Germany	1947	only	-	Jun	29	3:00	1:00	S
@@ -2269,7 +2272,7 @@ Zone Europe/Bucharest	1:44:24 -	LMT	1891 Oct
 # the State Duma has approved ... the draft bill on returning to
 # winter time standard and return Russia 11 time zones.  The new
 # regulations will come into effect on October 26, 2014 at 02:00 ...
-# http://asozd2.duma.gov.ru/main.nsf/(Spravka)?OpenAgent&RN=431985-6&02
+# http://asozd2.duma.gov.ru/main.nsf/%28Spravka%29?OpenAgent&RN=431985-6&02
 # Here is a link where we put together table (based on approved Bill N
 # 431985-6) with proposed 11 Russian time zones and corresponding
 # areas/cities/administrative centers in the Russian Federation (in English):
@@ -2679,13 +2682,13 @@ Zone Europe/Volgograd	 2:57:40 -	LMT	1920 Jan  3
 			 3:00	-	+03	1930 Jun 21
 			 4:00	-	+04	1961 Nov 11
 			 4:00	Russia	+04/+05	1988 Mar 27  2:00s
-			 3:00	Russia	MSK/MSD	1991 Mar 31  2:00s
+			 3:00	Russia	+03/+04	1991 Mar 31  2:00s
 			 4:00	-	+04	1992 Mar 29  2:00s
-			 3:00	Russia	MSK/MSD	2011 Mar 27  2:00s
-			 4:00	-	MSK	2014 Oct 26  2:00s
-			 3:00	-	MSK	2018 Oct 28  2:00s
+			 3:00	Russia	+03/+04	2011 Mar 27  2:00s
+			 4:00	-	+04	2014 Oct 26  2:00s
+			 3:00	-	+03	2018 Oct 28  2:00s
 			 4:00	-	+04	2020 Dec 27  2:00s
-			 3:00	-	MSK
+			 3:00	-	+03
 
 # From Paul Eggert (2016-11-11):
 # Europe/Saratov covers:
@@ -2716,11 +2719,11 @@ Zone Europe/Saratov	 3:04:18 -	LMT	1919 Jul  1  0:00u
 Zone Europe/Kirov	 3:18:48 -	LMT	1919 Jul  1  0:00u
 			 3:00	-	+03	1930 Jun 21
 			 4:00	Russia	+04/+05	1989 Mar 26  2:00s
-			 3:00	Russia	MSK/MSD	1991 Mar 31  2:00s
+			 3:00	Russia	+03/+04	1991 Mar 31  2:00s
 			 4:00	-	+04	1992 Mar 29  2:00s
-			 3:00	Russia	MSK/MSD	2011 Mar 27  2:00s
-			 4:00	-	MSK	2014 Oct 26  2:00s
-			 3:00	-	MSK
+			 3:00	Russia	+03/+04	2011 Mar 27  2:00s
+			 4:00	-	+04	2014 Oct 26  2:00s
+			 3:00	-	+03
 
 # From Tim Parenti (2014-07-03), per Oscar van Vlijmen (2001-08-25):
 # Europe/Samara covers...

make/data/tzdata/iso3166.tab

@@ -261,7 +261,7 @@ SY	Syria
 SZ	Eswatini (Swaziland)
 TC	Turks & Caicos Is
 TD	Chad
-TF	French S. Terr.
+TF	French Southern Territories
 TG	Togo
 TH	Thailand
 TJ	Tajikistan

make/data/tzdata/leapseconds

@@ -95,11 +95,11 @@ Leap	2016	Dec	31	23:59:60	+	S
 # Any additional leap seconds will come after this.
 # This Expires line is commented out for now,
 # so that pre-2020a zic implementations do not reject this file.
-#Expires 2023	Dec	28	00:00:00
+#Expires 2023	Jun	28	00:00:00
 
 # POSIX timestamps for the data in this file:
 #updated 1467936000 (2016-07-08 00:00:00 UTC)
-#expires 1703721600 (2023-12-28 00:00:00 UTC)
+#expires 1687910400 (2023-06-28 00:00:00 UTC)
 
-#	Updated through IERS Bulletin C65
-#	File expires on:  28 December 2023
+#	Updated through IERS Bulletin C64
+#	File expires on:  28 June 2023

make/data/tzdata/northamerica

@@ -1,3 +1,4 @@
+#
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -298,10 +299,9 @@ Zone	PST8PDT		 -8:00	US	P%sT
 #  -10	Standard Alaska Time (AST)	Alaska-Hawaii standard time (AHST)
 #  -11	(unofficial) Nome (NST)		Bering standard time (BST)
 #
-# From Paul Eggert (2023-01-23), from a 2001-01-08 heads-up from Rives McDow:
-# Public law 106-564 (2000-12-23) introduced "Chamorro standard time"
+# From Paul Eggert (2000-01-08), following a heads-up from Rives McDow:
+# Public law 106-564 (2000-12-23) introduced ... "Chamorro Standard Time"
 # for time in Guam and the Northern Marianas.  See the file "australasia".
-# Also see 15 U.S.C. §263 <https://www.law.cornell.edu/uscode/text/15/263>.
 #
 # From Paul Eggert (2015-04-17):
 # HST and HDT are standardized abbreviations for Hawaii-Aleutian
@@ -618,7 +618,7 @@ Zone America/Los_Angeles -7:52:58 -	LMT	1883 Nov 18 20:00u
 # local times of other Alaskan locations so that they change simultaneously.
 
 # From Paul Eggert (2014-07-18):
-# One opinion of the early 1980s turmoil in Alaska over time zones and
+# One opinion of the early-1980s turmoil in Alaska over time zones and
 # daylight saving time appeared as graffiti on a Juneau airport wall:
 # "Welcome to Juneau.  Please turn your watch back to the 19th century."
 # See: Turner W. Alaska's four time zones now two. NY Times 1983-11-01.
@@ -690,10 +690,6 @@ Zone America/Los_Angeles -7:52:58 -	LMT	1883 Nov 18 20:00u
 # So they won't be waiting for Alaska to join them on 2019-03-10, but will
 # rather change their clocks twice in seven weeks.
 
-# From Paul Eggert (2023-01-23):
-# America/Adak is for the Aleutian Islands that are part of Alaska
-# and are west of 169.5° W.
-
 # Zone	NAME		STDOFF	RULES	FORMAT	[UNTIL]
 Zone America/Juneau	 15:02:19 -	LMT	1867 Oct 19 15:33:32
 			 -8:57:41 -	LMT	1900 Aug 20 12:00
@@ -2152,6 +2148,10 @@ Zone America/Fort_Nelson	-8:10:47 -	LMT	1884
 # Nunavut ... moved ... to incorporate the whole territory into one time zone.
 # Nunavut moves to single time zone Oct. 31
 # http://www.nunatsiaq.com/nunavut/nvt90903_13.html
+#
+# From Antoine Leca (1999-09-06):
+# We then need to create a new timezone for the Kitikmeot region of Nunavut
+# to differentiate it from the Yellowknife region.
 
 # From Paul Eggert (1999-09-20):
 # Basic Facts: The New Territory
@@ -2345,6 +2345,9 @@ Zone America/Cambridge_Bay 0	-	-00	1920 # trading post est.?
 			-5:00	-	EST	2000 Nov  5  0:00
 			-6:00	-	CST	2001 Apr  1  3:00
 			-7:00	Canada	M%sT
+Zone America/Yellowknife 0	-	-00	1935 # Yellowknife founded?
+			-7:00	NT_YK	M%sT	1980
+			-7:00	Canada	M%sT
 Zone America/Inuvik	0	-	-00	1953 # Inuvik founded
 			-8:00	NT_YK	P%sT	1979 Apr lastSun  2:00
 			-7:00	NT_YK	M%sT	1980
@@ -2581,7 +2584,7 @@ Zone America/Dawson	-9:17:40 -	LMT	1900 Aug 20
 # and in addition changes all of Chihuahua to -06 with no DST.
 
 # From Heitor David Pinto (2022-11-28):
-# Now the northern [municipios] want to have the same time zone as the
+# Now the northern municipalities want to have the same time zone as the
 # respective neighboring cities in the US, for example Juárez in UTC-7 with
 # DST, matching El Paso, and Ojinaga in UTC-6 with DST, matching Presidio....
 # the president authorized the publication of the decree for November 29,
@@ -2618,7 +2621,7 @@ Zone America/Merida	-5:58:28 -	LMT	1922 Jan  1  6:00u
 			-5:00	-	EST	1982 Dec  2
 			-6:00	Mexico	C%sT
 # Coahuila, Nuevo León, Tamaulipas (near US border)
-# This includes the following municipios:
+# This includes the following municipalities:
 #   in Coahuila: Acuña, Allende, Guerrero, Hidalgo, Jiménez, Morelos, Nava,
 #     Ocampo, Piedras Negras, Villa Unión, Zaragoza
 #   in Nuevo León: Anáhuac
@@ -2644,8 +2647,8 @@ Zone America/Mexico_City -6:36:36 -	LMT	1922 Jan  1  7:00u
 			-6:00	-	CST	2002 Feb 20
 			-6:00	Mexico	C%sT
 # Chihuahua (near US border - western side)
-# This includes the municipios of Janos, Ascensión, Juárez, Guadalupe, and
-# Práxedis G Guerrero.
+# This includes the municipalities of Janos, Ascensión, Juárez, Guadalupe,
+# and Práxedis G Guerrero.
 # http://gaceta.diputados.gob.mx/PDF/65/2a022/nov/20221124-VII.pdf
 Zone America/Ciudad_Juarez -7:05:56 -	LMT	1922 Jan  1  7:00u
 			-7:00	-	MST	1927 Jun 10 23:00
@@ -2659,8 +2662,7 @@ Zone America/Ciudad_Juarez -7:05:56 -	LMT	1922 Jan  1  7:00u
 			-6:00	-	CST	2022 Nov 30  0:00
 			-7:00	US	M%sT
 # Chihuahua (near US border - eastern side)
-# This includes the municipios of Coyame del Sotol, Ojinaga, and Manuel
-# Benavides.
+# The municipalities of Coyame del Sotol, Ojinaga, and Manuel Benavides.
 # http://gaceta.diputados.gob.mx/PDF/65/2a022/nov/20221124-VII.pdf
 Zone America/Ojinaga	-6:57:40 -	LMT	1922 Jan  1  7:00u
 			-7:00	-	MST	1927 Jun 10 23:00
@@ -3081,7 +3083,7 @@ Zone America/Costa_Rica	-5:36:13 -	LMT	1890        # San José
 #
 # He supplied these references:
 #
-# http://www.prensalatina.com.mx/article.asp?ID={4CC32C1B-A9F7-42FB-8A07-8631AFC923AF}&language=ES
+# http://www.prensalatina.com.mx/article.asp?ID=%7B4CC32C1B-A9F7-42FB-8A07-8631AFC923AF%7D&language=ES
 # http://actualidad.terra.es/sociedad/articulo/cuba_llama_ahorrar_energia_cambio_1957044.htm
 #
 # From Alex Krivenyshev (2007-10-25):

make/data/tzdata/southamerica

@@ -231,7 +231,7 @@ Rule	Arg	2008	only	-	Oct	Sun>=15	0:00	1:00	-
 # Hora de verano para la República Argentina
 # http://buenasiembra.com.ar/esoterismo/astrologia/hora-de-verano-de-la-republica-argentina-27.html
 # says that standard time in Argentina from 1894-10-31
-# to 1920-05-01 was -4:16:48.25.  Go with this more precise value
+# to 1920-05-01 was -4:16:48.25.  Go with this more-precise value
 # over Shanks & Pottenger.  It is upward compatible with Milne, who
 # says Córdoba time was -4:16:48.2.
 

make/data/tzdata/zone.tab

@@ -144,8 +144,9 @@ CA	+744144-0944945	America/Resolute	Central - NU (Resolute)
 CA	+624900-0920459	America/Rankin_Inlet	Central - NU (central)
 CA	+5024-10439	America/Regina	CST - SK (most areas)
 CA	+5017-10750	America/Swift_Current	CST - SK (midwest)
-CA	+5333-11328	America/Edmonton	Mountain - AB; BC (E); NT (E); SK (W)
+CA	+5333-11328	America/Edmonton	Mountain - AB; BC (E); SK (W)
 CA	+690650-1050310	America/Cambridge_Bay	Mountain - NU (west)
+CA	+6227-11421	America/Yellowknife	Mountain - NT (central)
 CA	+682059-1334300	America/Inuvik	Mountain - NT (west)
 CA	+4906-11631	America/Creston	MST - BC (Creston)
 CA	+5546-12014	America/Dawson_Creek	MST - BC (Dawson Cr, Ft St John)
@@ -161,7 +162,7 @@ CG	-0416+01517	Africa/Brazzaville
 CH	+4723+00832	Europe/Zurich
 CI	+0519-00402	Africa/Abidjan
 CK	-2114-15946	Pacific/Rarotonga
-CL	-3327-07040	America/Santiago	most of Chile
+CL	-3327-07040	America/Santiago	Chile (most areas)
 CL	-5309-07055	America/Punta_Arenas	Region of Magallanes
 CL	-2709-10926	Pacific/Easter	Easter Island
 CM	+0403+00942	Africa/Douala
@@ -173,10 +174,10 @@ CU	+2308-08222	America/Havana
 CV	+1455-02331	Atlantic/Cape_Verde
 CW	+1211-06900	America/Curacao
 CX	-1025+10543	Indian/Christmas
-CY	+3510+03322	Asia/Nicosia	most of Cyprus
+CY	+3510+03322	Asia/Nicosia	Cyprus (most areas)
 CY	+3507+03357	Asia/Famagusta	Northern Cyprus
 CZ	+5005+01426	Europe/Prague
-DE	+5230+01322	Europe/Berlin	most of Germany
+DE	+5230+01322	Europe/Berlin	Germany (most areas)
 DE	+4742+00841	Europe/Busingen	Busingen
 DJ	+1136+04309	Africa/Djibouti
 DK	+5540+01235	Europe/Copenhagen
@@ -209,7 +210,7 @@ GF	+0456-05220	America/Cayenne
 GG	+492717-0023210	Europe/Guernsey
 GH	+0533-00013	Africa/Accra
 GI	+3608-00521	Europe/Gibraltar
-GL	+6411-05144	America/Nuuk	most of Greenland
+GL	+6411-05144	America/Nuuk	Greenland (most areas)
 GL	+7646-01840	America/Danmarkshavn	National Park (east coast)
 GL	+7029-02158	America/Scoresbysund	Scoresbysund/Ittoqqortoormiit
 GL	+7634-06847	America/Thule	Thule/Pituffik
@@ -257,7 +258,7 @@ KP	+3901+12545	Asia/Pyongyang
 KR	+3733+12658	Asia/Seoul
 KW	+2920+04759	Asia/Kuwait
 KY	+1918-08123	America/Cayman
-KZ	+4315+07657	Asia/Almaty	most of Kazakhstan
+KZ	+4315+07657	Asia/Almaty	Kazakhstan (most areas)
 KZ	+4448+06528	Asia/Qyzylorda	Qyzylorda/Kyzylorda/Kzyl-Orda
 KZ	+5312+06337	Asia/Qostanay	Qostanay/Kostanay/Kustanay
 KZ	+5017+05710	Asia/Aqtobe	Aqtobe/Aktobe
@@ -281,12 +282,12 @@ MD	+4700+02850	Europe/Chisinau
 ME	+4226+01916	Europe/Podgorica
 MF	+1804-06305	America/Marigot
 MG	-1855+04731	Indian/Antananarivo
-MH	+0709+17112	Pacific/Majuro	most of Marshall Islands
+MH	+0709+17112	Pacific/Majuro	Marshall Islands (most areas)
 MH	+0905+16720	Pacific/Kwajalein	Kwajalein
 MK	+4159+02126	Europe/Skopje
 ML	+1239-00800	Africa/Bamako
 MM	+1647+09610	Asia/Yangon
-MN	+4755+10653	Asia/Ulaanbaatar	most of Mongolia
+MN	+4755+10653	Asia/Ulaanbaatar	Mongolia (most areas)
 MN	+4801+09139	Asia/Hovd	Bayan-Olgiy, Govi-Altai, Hovd, Uvs, Zavkhan
 MN	+4804+11430	Asia/Choibalsan	Dornod, Sukhbaatar
 MO	+221150+1133230	Asia/Macau
@@ -324,7 +325,7 @@ NO	+5955+01045	Europe/Oslo
 NP	+2743+08519	Asia/Kathmandu
 NR	-0031+16655	Pacific/Nauru
 NU	-1901-16955	Pacific/Niue
-NZ	-3652+17446	Pacific/Auckland	most of New Zealand
+NZ	-3652+17446	Pacific/Auckland	New Zealand (most areas)
 NZ	-4357-17633	Pacific/Chatham	Chatham Islands
 OM	+2336+05835	Asia/Muscat
 PA	+0858-07932	America/Panama
@@ -332,7 +333,7 @@ PE	-1203-07703	America/Lima
 PF	-1732-14934	Pacific/Tahiti	Society Islands
 PF	-0900-13930	Pacific/Marquesas	Marquesas Islands
 PF	-2308-13457	Pacific/Gambier	Gambier Islands
-PG	-0930+14710	Pacific/Port_Moresby	most of Papua New Guinea
+PG	-0930+14710	Pacific/Port_Moresby	Papua New Guinea (most areas)
 PG	-0613+15534	Pacific/Bougainville	Bougainville
 PH	+1435+12100	Asia/Manila
 PK	+2452+06703	Asia/Karachi
@@ -378,7 +379,7 @@ RU	+4310+13156	Asia/Vladivostok	MSK+07 - Amur River
 RU	+643337+1431336	Asia/Ust-Nera	MSK+07 - Oymyakonsky
 RU	+5934+15048	Asia/Magadan	MSK+08 - Magadan
 RU	+4658+14242	Asia/Sakhalin	MSK+08 - Sakhalin Island
-RU	+6728+15343	Asia/Srednekolymsk	MSK+08 - Sakha (E); N Kuril Is
+RU	+6728+15343	Asia/Srednekolymsk	MSK+08 - Sakha (E); North Kuril Is
 RU	+5301+15839	Asia/Kamchatka	MSK+09 - Kamchatka
 RU	+6445+17729	Asia/Anadyr	MSK+09 - Bering Sea
 RW	-0157+03004	Africa/Kigali
@@ -419,7 +420,7 @@ TT	+1039-06131	America/Port_of_Spain
 TV	-0831+17913	Pacific/Funafuti
 TW	+2503+12130	Asia/Taipei
 TZ	-0648+03917	Africa/Dar_es_Salaam
-UA	+5026+03031	Europe/Kyiv	most of Ukraine
+UA	+5026+03031	Europe/Kyiv	Ukraine (most areas)
 UG	+0019+03225	Africa/Kampala
 UM	+2813-17722	Pacific/Midway	Midway Islands
 UM	+1917+16637	Pacific/Wake	Wake Island
@@ -442,7 +443,7 @@ US	+465042-1012439	America/North_Dakota/New_Salem	Central - ND (Morton rural)
 US	+471551-1014640	America/North_Dakota/Beulah	Central - ND (Mercer)
 US	+394421-1045903	America/Denver	Mountain (most areas)
 US	+433649-1161209	America/Boise	Mountain - ID (south); OR (east)
-US	+332654-1120424	America/Phoenix	MST - AZ (except Navajo)
+US	+332654-1120424	America/Phoenix	MST - Arizona (except Navajo)
 US	+340308-1181434	America/Los_Angeles	Pacific
 US	+611305-1495401	America/Anchorage	Alaska (most areas)
 US	+581807-1342511	America/Juneau	Alaska - Juneau area
@@ -450,7 +451,7 @@ US	+571035-1351807	America/Sitka	Alaska - Sitka area
 US	+550737-1313435	America/Metlakatla	Alaska - Annette Island
 US	+593249-1394338	America/Yakutat	Alaska - Yakutat
 US	+643004-1652423	America/Nome	Alaska (west)
-US	+515248-1763929	America/Adak	Alaska - western Aleutians
+US	+515248-1763929	America/Adak	Aleutian Islands
 US	+211825-1575130	Pacific/Honolulu	Hawaii
 UY	-345433-0561245	America/Montevideo
 UZ	+3940+06648	Asia/Samarkand	Uzbekistan (west)

make/devkit/Tools.gmk

@@ -87,17 +87,8 @@ endif
 # Define external dependencies
 
 # Latest that could be made to work.
-GCC_VER := 11.2.0
-ifeq ($(GCC_VER), 11.2.0)
-  gcc_ver := gcc-11.2.0
-  binutils_ver := binutils-2.37
-  ccache_ver := ccache-3.7.12
-  mpfr_ver := mpfr-4.1.0
-  gmp_ver := gmp-6.2.1
-  mpc_ver := mpc-1.2.1
-  gdb_ver := gdb-11.1
-  REQUIRED_MIN_MAKE_MAJOR_VERSION := 4
-else ifeq ($(GCC_VER), 10.3.0)
+GCC_VER := 10.3.0
+ifeq ($(GCC_VER), 10.3.0)
   gcc_ver := gcc-10.3.0
   binutils_ver := binutils-2.36.1
   ccache_ver := ccache-3.7.11

make/hotspot/gensrc/GensrcAdlc.gmk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013, 2022, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2013, 2021, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -149,13 +149,6 @@ ifeq ($(call check-jvm-feature, compiler2), true)
     )))
   endif
 
-  ifeq ($(HOTSPOT_TARGET_CPU_ARCH), riscv)
-    AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \
-        $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_CPU_ARCH)_v.ad \
-        $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_CPU_ARCH)_b.ad \
-    )))
-  endif
-
   ifeq ($(call check-jvm-feature, shenandoahgc), true)
     AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \
         $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \

make/hotspot/lib/CompileGtest.gmk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -49,7 +49,7 @@ $(eval $(call SetupJdkLibrary, BUILD_GTEST_LIBGTEST, \
         $(GTEST_FRAMEWORK_SRC)/googletest/src \
         $(GTEST_FRAMEWORK_SRC)/googlemock/src, \
     INCLUDE_FILES := gtest-all.cc gmock-all.cc, \
-    DISABLED_WARNINGS_gcc := undef unused-result format-nonliteral maybe-uninitialized, \
+    DISABLED_WARNINGS_gcc := undef unused-result format-nonliteral, \
     DISABLED_WARNINGS_clang := undef unused-result format-nonliteral, \
     CFLAGS := $(JVM_CFLAGS) \
         -I$(GTEST_FRAMEWORK_SRC)/googletest \

make/jdk/src/classes/build/tools/charsetmapping/SPI.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, 2023, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -50,19 +50,18 @@ public class SPI {
                         out.println(line);
                     } else {
                         charsets.values()
-                            .stream()
-                            .filter(cs -> cs.pkgName.equals("sun.nio.cs.ext") &&
-                                          !cs.isInternal &&
-                                          (cs.os == null || cs.os.equals(os)))
-                            .forEach( cs -> {
-                                out.printf("        charset(\"%s\", \"%s\",%n", cs.csName, cs.clzName);
-                                out.printf("                new String[] {%n");
-                                for (String alias : cs.aliases) {
-                                    out.printf("                    \"%s\",%n",
-                                            alias);
-                                }
-                                out.printf("                });%n%n");
-                            });
+                                .stream()
+                                .filter(cs -> cs.pkgName.equals("sun.nio.cs.ext") &&
+                                              !cs.isInternal &&
+                                              (cs.os == null || cs.os.equals(os)))
+                                .forEach( cs -> {
+                            out.printf("        charset(\"%s\", \"%s\",%n", cs.csName, cs.clzName);
+                            out.printf("                new String[] {%n");
+                            for (String alias : cs.aliases) {
+                                out.printf("                    \"%s\",%n", alias);
+                            }
+                            out.printf("                });%n%n");
+                        });
                     }
                 }
             } else if (type.startsWith("stdcs")) {    // StandardCharsets.java
@@ -94,15 +93,8 @@ public class SPI {
                                  .filter(cs -> cs.pkgName.equals("sun.nio.cs"))
                                  .forEach( cs -> {
                              if (cs.aliases == null || cs.aliases.length == 0) {
-                                 if (cs.csName.equals("GB18030")) {
-                                     out.printf("    static String[] aliases_GB18030() { return new String[] {%n");
-                                     out.printf("            GB18030.IS_2000 ? \"gb18030-2000\" : \"gb18030-2022\"%n");
-                                     out.printf("        };%n");
-                                     out.printf("    }%n%n");
-                                 } else {
-                                     out.printf("    static String[] aliases_%s() { return null; }%n%n",
-                                             cs.clzName);
-                                 }
+                                 out.printf("    static String[] aliases_%s() { return null; }%n%n",
+                                            cs.clzName);
                              } else {
                                  boolean methodEnd = true;
                                  // non-final for SJIS and MS932 to support sun.nio.cs.map

make/jdk/src/classes/build/tools/cldrconverter/Bundle.java

@@ -197,7 +197,9 @@ class Bundle {
         // parentsMap contains resources from id's parents.
         Map<String, Object> parentsMap = new HashMap<>();
         for (int i = cldrBundles.length - 1; i > index; i--) {
-            parentsMap.putAll(CLDRConverter.getCLDRBundle(cldrBundles[i]));
+            if (!("no".equals(cldrBundles[i]) || cldrBundles[i].startsWith("no_"))) {
+                parentsMap.putAll(CLDRConverter.getCLDRBundle(cldrBundles[i]));
+            }
         }
         // Duplicate myMap as parentsMap for "root" so that the
         // fallback works. This is a hack, though.

make/modules/java.base/lib/CoreLibraries.gmk

@@ -49,7 +49,6 @@ $(eval $(call SetupNativeCompilation, BUILD_LIBFDLIBM, \
     CFLAGS_windows_debug := -DLOGGING, \
     CFLAGS_aix := -qfloat=nomaf, \
     DISABLED_WARNINGS_gcc := sign-compare misleading-indentation array-bounds, \
-    DISABLED_WARNINGS_gcc_k_rem_pio2.c := maybe-uninitialized, \
     DISABLED_WARNINGS_clang := sign-compare misleading-indentation, \
     DISABLED_WARNINGS_microsoft := 4146 4244 4018, \
     ARFLAGS := $(ARFLAGS), \

make/modules/java.desktop/lib/Awt2dLibraries.gmk

@@ -504,7 +504,7 @@ else
                         -DHB_NO_PRAGMA_GCC_DIAGNOSTIC
    endif
    ifeq ($(call isTargetOs, linux macosx), true)
-     HARFBUZZ_CFLAGS += -DHAVE_INTEL_ATOMIC_PRIMITIVES -DHB_NO_VISIBILITY
+     HARFBUZZ_CFLAGS += -DHAVE_INTEL_ATOMIC_PRIMITIVES
    endif
 
    # Early re-canonizing has to be disabled to workaround an internal XlC compiler error
@@ -517,9 +517,8 @@ else
    LIBFONTMANAGER_EXCLUDE_FILES += libharfbuzz/hb-ft.cc
 
    HARFBUZZ_DISABLED_WARNINGS_gcc := type-limits missing-field-initializers strict-aliasing
-   # noexcept-type required for GCC 7 builds. Not required for GCC 8+.
    HARFBUZZ_DISABLED_WARNINGS_CXX_gcc := reorder delete-non-virtual-dtor strict-overflow \
-        maybe-uninitialized class-memaccess unused-result extra use-after-free noexcept-type
+        maybe-uninitialized class-memaccess unused-result extra use-after-free
    HARFBUZZ_DISABLED_WARNINGS_clang := unused-value incompatible-pointer-types \
         tautological-constant-out-of-range-compare int-to-pointer-cast \
         undef missing-field-initializers range-loop-analysis \
@@ -560,10 +559,12 @@ ifeq ($(call isTargetOs, windows), true)
 else ifeq ($(call isTargetOs, macosx), true)
   LIBFONTMANAGER_EXCLUDE_FILES += X11FontScaler.c \
       X11TextRenderer.c \
+      fontpath.c \
       lcdglyph.c \
       lcdglyphDW.cpp
 else
-  LIBFONTMANAGER_EXCLUDE_FILES += lcdglyph.c \
+  LIBFONTMANAGER_EXCLUDE_FILES += fontpath.c \
+      lcdglyph.c \
       lcdglyphDW.cpp
 endif
 

make/modules/jdk.internal.vm.ci/Java.gmk

@@ -26,5 +26,13 @@
 # -parameters provides method's parameters information in class file,
 # JVMCI compilers make use of that information for various sanity checks.
 # Don't use Indy strings concatenation to have good JVMCI startup performance.
+# The exports are needed since JVMCI is dynamically exported (see
+# jdk.vm.ci.services.internal.ReflectionAccessJDK::openJVMCITo).
 
 JAVAC_FLAGS += -parameters -XDstringConcat=inline
+
+## WORKAROUND jdk.internal.vm.ci source structure issue
+JVMCI_MODULESOURCEPATH := $(MODULESOURCEPATH) \
+	$(subst /$(MODULE)/,/*/, $(filter-out %processor/src, \
+		$(wildcard $(TOPDIR)/src/$(MODULE)/share/classes/*/src)))
+MODULESOURCEPATH := $(call PathList, $(JVMCI_MODULESOURCEPATH))

make/test/JtregNativeHotspot.gmk

@@ -871,7 +871,7 @@ BUILD_HOTSPOT_JTREG_EXECUTABLES_LIBS_exesigtest := -ljvm
 
 ifeq ($(call isTargetOs, windows), true)
     BUILD_HOTSPOT_JTREG_EXECUTABLES_CFLAGS_exeFPRegs := -MT
-    BUILD_HOTSPOT_JTREG_EXCLUDE += exesigtest.c libterminatedThread.c libTestJNI.c libnativeStack.c
+    BUILD_HOTSPOT_JTREG_EXCLUDE += exesigtest.c libterminatedThread.c libTestJNI.c
     BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libatExit := jvm.lib
 else
     BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libbootclssearch_agent += -lpthread
@@ -1508,7 +1508,6 @@ else
     BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libgetphase002 += -lpthread
     BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libterminatedThread += -lpthread
     BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libatExit += -ljvm
-    BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libnativeStack += -lpthread
 endif
 
 # This evaluation is expensive and should only be done if this target was

src/hotspot/cpu/aarch64/aarch64.ad

@@ -8646,7 +8646,6 @@ instruct membar_release() %{
 
 instruct membar_storestore() %{
   match(MemBarStoreStore);
-  match(StoreStoreFence);
   ins_cost(VOLATILE_REF_COST);
 
   format %{ "MEMBAR-store-store" %}
@@ -17029,17 +17028,16 @@ instruct string_compress(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
                          iRegI_R0 result, rFlagsReg cr)
 %{
   match(Set result (StrCompressedCopy src (Binary dst len)));
-  effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4,
-         USE_KILL src, USE_KILL dst, USE len, KILL cr);
+  effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
 
-  format %{ "String Compress $src,$dst,$len -> $result  // KILL $src,$dst" %}
+  format %{ "String Compress $src,$dst -> $result    // KILL R1, R2, R3, R4" %}
   ins_encode %{
     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
-                           $result$$Register,
                            $tmp1$$FloatRegister, $tmp2$$FloatRegister,
-                           $tmp3$$FloatRegister, $tmp4$$FloatRegister);
+                           $tmp3$$FloatRegister, $tmp4$$FloatRegister,
+                           $result$$Register);
   %}
-  ins_pipe(pipe_slow);
+  ins_pipe( pipe_slow );
 %}
 
 // fast byte[] to char[] inflation
@@ -17064,43 +17062,22 @@ instruct string_inflate(Universe dummy, iRegP_R0 src, iRegP_R1 dst, iRegI_R2 len
 
 // encode char[] to byte[] in ISO_8859_1
 instruct encode_iso_array(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
-                          vRegD_V0 vtmp0, vRegD_V1 vtmp1,
-                          vRegD_V2 vtmp2, vRegD_V3 vtmp3,
+                          vRegD_V0 Vtmp1, vRegD_V1 Vtmp2,
+                          vRegD_V2 Vtmp3, vRegD_V3 Vtmp4,
                           iRegI_R0 result, rFlagsReg cr)
 %{
   predicate(!((EncodeISOArrayNode*)n)->is_ascii());
   match(Set result (EncodeISOArray src (Binary dst len)));
-  effect(USE_KILL src, USE_KILL dst, USE len,
-         KILL vtmp0, KILL vtmp1, KILL vtmp2, KILL vtmp3, KILL cr);
+  effect(USE_KILL src, USE_KILL dst, USE_KILL len,
+         KILL Vtmp1, KILL Vtmp2, KILL Vtmp3, KILL Vtmp4, KILL cr);
 
-  format %{ "Encode ISO array $src,$dst,$len -> $result" %}
+  format %{ "Encode array $src,$dst,$len -> $result" %}
   ins_encode %{
     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
-                        $result$$Register, false,
-                        $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
-                        $vtmp2$$FloatRegister, $vtmp3$$FloatRegister);
+         $result$$Register, $Vtmp1$$FloatRegister,  $Vtmp2$$FloatRegister,
+         $Vtmp3$$FloatRegister,  $Vtmp4$$FloatRegister);
   %}
-  ins_pipe(pipe_class_memory);
-%}
-
-instruct encode_ascii_array(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
-                            vRegD_V0 vtmp0, vRegD_V1 vtmp1,
-                            vRegD_V2 vtmp2, vRegD_V3 vtmp3,
-                            iRegI_R0 result, rFlagsReg cr)
-%{
-  predicate(((EncodeISOArrayNode*)n)->is_ascii());
-  match(Set result (EncodeISOArray src (Binary dst len)));
-  effect(USE_KILL src, USE_KILL dst, USE len,
-         KILL vtmp0, KILL vtmp1, KILL vtmp2, KILL vtmp3, KILL cr);
-
-  format %{ "Encode ASCII array $src,$dst,$len -> $result" %}
-  ins_encode %{
-    __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
-                        $result$$Register, true,
-                        $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
-                        $vtmp2$$FloatRegister, $vtmp3$$FloatRegister);
-  %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe( pipe_class_memory );
 %}
 
 // ============================================================================

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@@ -2448,12 +2448,6 @@ public:
   INSN(cnt,    0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
   INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
   INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
-  // Zero compare.
-  INSN(cmeq,   0, 0b100000100110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
-  INSN(cmge,   1, 0b100000100010, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
-  INSN(cmgt,   0, 0b100000100010, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
-  INSN(cmle,   1, 0b100000100110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
-  INSN(cmlt,   0, 0b100000101010, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
 
 #undef INSN
 

src/hotspot/cpu/aarch64/atomic_aarch64.hpp

@@ -37,8 +37,6 @@ typedef uint64_t (*aarch64_atomic_stub_t)(volatile void *ptr, uint64_t arg1, uin
 // Pointers to stubs
 extern aarch64_atomic_stub_t aarch64_atomic_fetch_add_4_impl;
 extern aarch64_atomic_stub_t aarch64_atomic_fetch_add_8_impl;
-extern aarch64_atomic_stub_t aarch64_atomic_fetch_add_4_relaxed_impl;
-extern aarch64_atomic_stub_t aarch64_atomic_fetch_add_8_relaxed_impl;
 extern aarch64_atomic_stub_t aarch64_atomic_xchg_4_impl;
 extern aarch64_atomic_stub_t aarch64_atomic_xchg_8_impl;
 extern aarch64_atomic_stub_t aarch64_atomic_cmpxchg_1_impl;

src/hotspot/cpu/aarch64/jvmciCodeInstaller_aarch64.cpp

@@ -138,21 +138,21 @@ void CodeInstaller::pd_relocate_JavaMethod(CodeBuffer &cbuf, JVMCIObject hotspot
       assert(method == NULL || !method->is_static(), "cannot call static method with invokeinterface");
       NativeCall* call = nativeCall_at(_instructions->start() + pc_offset);
       _instructions->relocate(call->instruction_address(), virtual_call_Relocation::spec(_invoke_mark_pc));
-      call->trampoline_jump(cbuf, SharedRuntime::get_resolve_virtual_call_stub(), JVMCI_CHECK);
+      call->trampoline_jump(cbuf, SharedRuntime::get_resolve_virtual_call_stub());
       break;
     }
     case INVOKESTATIC: {
       assert(method == NULL || method->is_static(), "cannot call non-static method with invokestatic");
       NativeCall* call = nativeCall_at(_instructions->start() + pc_offset);
       _instructions->relocate(call->instruction_address(), relocInfo::static_call_type);
-      call->trampoline_jump(cbuf, SharedRuntime::get_resolve_static_call_stub(), JVMCI_CHECK);
+      call->trampoline_jump(cbuf, SharedRuntime::get_resolve_static_call_stub());
       break;
     }
     case INVOKESPECIAL: {
       assert(method == NULL || !method->is_static(), "cannot call static method with invokespecial");
       NativeCall* call = nativeCall_at(_instructions->start() + pc_offset);
       _instructions->relocate(call->instruction_address(), relocInfo::opt_virtual_call_type);
-      call->trampoline_jump(cbuf, SharedRuntime::get_resolve_opt_virtual_call_stub(), JVMCI_CHECK);
+      call->trampoline_jump(cbuf, SharedRuntime::get_resolve_opt_virtual_call_stub());
       break;
     }
     default:

src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp

@@ -5031,119 +5031,112 @@ void MacroAssembler::fill_words(Register base, Register cnt, Register value)
   bind(fini);
 }
 
-// Intrinsic for
-//
-// - sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray
-//     return the number of characters copied.
-// - java/lang/StringUTF16.compress
-//     return zero (0) if copy fails, otherwise 'len'.
-//
-// This version always returns the number of characters copied, and does not
-// clobber the 'len' register. A successful copy will complete with the post-
-// condition: 'res' == 'len', while an unsuccessful copy will exit with the
-// post-condition: 0 <= 'res' < 'len'.
-//
-// NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
-//       degrade performance (on Ampere Altra - Neoverse N1), to an extent
-//       beyond the acceptable, even though the footprint would be smaller.
-//       Using 'umaxv' in the ASCII-case comes with a small penalty but does
-//       avoid additional bloat.
-//
+// Intrinsic for sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray and
+// java/lang/StringUTF16.compress.
 void MacroAssembler::encode_iso_array(Register src, Register dst,
-                                      Register len, Register res, bool ascii,
-                                      FloatRegister vtmp0, FloatRegister vtmp1,
-                                      FloatRegister vtmp2, FloatRegister vtmp3)
+                      Register len, Register result,
+                      FloatRegister Vtmp1, FloatRegister Vtmp2,
+                      FloatRegister Vtmp3, FloatRegister Vtmp4)
 {
-  Register cnt = res;
-  Register max = rscratch1;
-  Register chk = rscratch2;
+    Label DONE, SET_RESULT, NEXT_32, NEXT_32_PRFM, LOOP_8, NEXT_8, LOOP_1, NEXT_1,
+        NEXT_32_START, NEXT_32_PRFM_START;
+    Register tmp1 = rscratch1, tmp2 = rscratch2;
 
-  prfm(Address(src), PLDL1STRM);
-  movw(cnt, len);
+      mov(result, len); // Save initial len
 
-#define ASCII(insn) do { if (ascii) { insn; } } while (0)
+      cmp(len, (u1)8); // handle shortest strings first
+      br(LT, LOOP_1);
+      cmp(len, (u1)32);
+      br(LT, NEXT_8);
+      // The following code uses the SIMD 'uzp1' and 'uzp2' instructions
+      // to convert chars to bytes
+      if (SoftwarePrefetchHintDistance >= 0) {
+        ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
+        subs(tmp2, len, SoftwarePrefetchHintDistance/2 + 16);
+        br(LE, NEXT_32_START);
+        b(NEXT_32_PRFM_START);
+        BIND(NEXT_32_PRFM);
+          ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
+        BIND(NEXT_32_PRFM_START);
+          prfm(Address(src, SoftwarePrefetchHintDistance));
+          orr(v4, T16B, Vtmp1, Vtmp2);
+          orr(v5, T16B, Vtmp3, Vtmp4);
+          uzp1(Vtmp1, T16B, Vtmp1, Vtmp2);
+          uzp1(Vtmp3, T16B, Vtmp3, Vtmp4);
+          uzp2(v5, T16B, v4, v5); // high bytes
+          umov(tmp2, v5, D, 1);
+          fmovd(tmp1, v5);
+          orr(tmp1, tmp1, tmp2);
+          cbnz(tmp1, LOOP_8);
+          stpq(Vtmp1, Vtmp3, dst);
+          sub(len, len, 32);
+          add(dst, dst, 32);
+          add(src, src, 64);
+          subs(tmp2, len, SoftwarePrefetchHintDistance/2 + 16);
+          br(GE, NEXT_32_PRFM);
+          cmp(len, (u1)32);
+          br(LT, LOOP_8);
+        BIND(NEXT_32);
+          ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
+        BIND(NEXT_32_START);
+      } else {
+        BIND(NEXT_32);
+          ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
+      }
+      prfm(Address(src, SoftwarePrefetchHintDistance));
+      uzp1(v4, T16B, Vtmp1, Vtmp2);
+      uzp1(v5, T16B, Vtmp3, Vtmp4);
+      orr(Vtmp1, T16B, Vtmp1, Vtmp2);
+      orr(Vtmp3, T16B, Vtmp3, Vtmp4);
+      uzp2(Vtmp1, T16B, Vtmp1, Vtmp3); // high bytes
+      umov(tmp2, Vtmp1, D, 1);
+      fmovd(tmp1, Vtmp1);
+      orr(tmp1, tmp1, tmp2);
+      cbnz(tmp1, LOOP_8);
+      stpq(v4, v5, dst);
+      sub(len, len, 32);
+      add(dst, dst, 32);
+      add(src, src, 64);
+      cmp(len, (u1)32);
+      br(GE, NEXT_32);
+      cbz(len, DONE);
 
-  Label LOOP_32, DONE_32, FAIL_32;
+    BIND(LOOP_8);
+      cmp(len, (u1)8);
+      br(LT, LOOP_1);
+    BIND(NEXT_8);
+      ld1(Vtmp1, T8H, src);
+      uzp1(Vtmp2, T16B, Vtmp1, Vtmp1); // low bytes
+      uzp2(Vtmp3, T16B, Vtmp1, Vtmp1); // high bytes
+      fmovd(tmp1, Vtmp3);
+      cbnz(tmp1, NEXT_1);
+      strd(Vtmp2, dst);
 
-  BIND(LOOP_32);
-  {
-    cmpw(cnt, 32);
-    br(LT, DONE_32);
-    ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
-    // Extract lower bytes.
-    FloatRegister vlo0 = v4;
-    FloatRegister vlo1 = v5;
-    uzp1(vlo0, T16B, vtmp0, vtmp1);
-    uzp1(vlo1, T16B, vtmp2, vtmp3);
-    // Merge bits...
-    orr(vtmp0, T16B, vtmp0, vtmp1);
-    orr(vtmp2, T16B, vtmp2, vtmp3);
-    // Extract merged upper bytes.
-    FloatRegister vhix = vtmp0;
-    uzp2(vhix, T16B, vtmp0, vtmp2);
-    // ISO-check on hi-parts (all zero).
-    //                          ASCII-check on lo-parts (no sign).
-    FloatRegister vlox = vtmp1; // Merge lower bytes.
-                                ASCII(orr(vlox, T16B, vlo0, vlo1));
-    umov(chk, vhix, D, 1);      ASCII(cmlt(vlox, T16B, vlox));
-    fmovd(max, vhix);           ASCII(umaxv(vlox, T16B, vlox));
-    orr(chk, chk, max);         ASCII(umov(max, vlox, B, 0));
-                                ASCII(orr(chk, chk, max));
-    cbnz(chk, FAIL_32);
-    subw(cnt, cnt, 32);
-    st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
-    b(LOOP_32);
-  }
-  BIND(FAIL_32);
-  sub(src, src, 64);
-  BIND(DONE_32);
+      sub(len, len, 8);
+      add(dst, dst, 8);
+      add(src, src, 16);
+      cmp(len, (u1)8);
+      br(GE, NEXT_8);
 
-  Label LOOP_8, SKIP_8;
+    BIND(LOOP_1);
 
-  BIND(LOOP_8);
-  {
-    cmpw(cnt, 8);
-    br(LT, SKIP_8);
-    FloatRegister vhi = vtmp0;
-    FloatRegister vlo = vtmp1;
-    ld1(vtmp3, T8H, src);
-    uzp1(vlo, T16B, vtmp3, vtmp3);
-    uzp2(vhi, T16B, vtmp3, vtmp3);
-    // ISO-check on hi-parts (all zero).
-    //                          ASCII-check on lo-parts (no sign).
-                                ASCII(cmlt(vtmp2, T16B, vlo));
-    fmovd(chk, vhi);            ASCII(umaxv(vtmp2, T16B, vtmp2));
-                                ASCII(umov(max, vtmp2, B, 0));
-                                ASCII(orr(chk, chk, max));
-    cbnz(chk, SKIP_8);
+    cbz(len, DONE);
+    BIND(NEXT_1);
+      ldrh(tmp1, Address(post(src, 2)));
+      tst(tmp1, 0xff00);
+      br(NE, SET_RESULT);
+      strb(tmp1, Address(post(dst, 1)));
+      subs(len, len, 1);
+      br(GT, NEXT_1);
 
-    strd(vlo, Address(post(dst, 8)));
-    subw(cnt, cnt, 8);
-    add(src, src, 16);
-    b(LOOP_8);
-  }
-  BIND(SKIP_8);
-
-#undef ASCII
-
-  Label LOOP, DONE;
-
-  cbz(cnt, DONE);
-  BIND(LOOP);
-  {
-    Register chr = rscratch1;
-    ldrh(chr, Address(post(src, 2)));
-    tst(chr, ascii ? 0xff80 : 0xff00);
-    br(NE, DONE);
-    strb(chr, Address(post(dst, 1)));
-    subs(cnt, cnt, 1);
-    br(GT, LOOP);
-  }
-  BIND(DONE);
-  // Return index where we stopped.
-  subw(res, len, cnt);
+    BIND(SET_RESULT);
+      sub(result, result, len); // Return index where we stopped
+                                // Return len == 0 if we processed all
+                                // characters
+    BIND(DONE);
 }
 
+
 // Inflate byte[] array to char[].
 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
                                            FloatRegister vtmp1, FloatRegister vtmp2,
@@ -5251,13 +5244,13 @@ address MacroAssembler::byte_array_inflate(Register src, Register dst, Register
 
 // Compress char[] array to byte[].
 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
-                                         Register res,
-                                         FloatRegister tmp0, FloatRegister tmp1,
-                                         FloatRegister tmp2, FloatRegister tmp3) {
-  encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3);
-  // Adjust result: res == len ? len : 0
-  cmp(len, res);
-  csel(res, res, zr, EQ);
+                                         FloatRegister tmp1Reg, FloatRegister tmp2Reg,
+                                         FloatRegister tmp3Reg, FloatRegister tmp4Reg,
+                                         Register result) {
+  encode_iso_array(src, dst, len, result,
+                   tmp1Reg, tmp2Reg, tmp3Reg, tmp4Reg);
+  cmp(len, zr);
+  csel(result, result, zr, EQ);
 }
 
 // get_thread() can be called anywhere inside generated code so we

src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp

@@ -1273,15 +1273,14 @@ public:
                              FloatRegister vtmp3, Register tmp4);
 
   void char_array_compress(Register src, Register dst, Register len,
-                           Register res,
-                           FloatRegister vtmp0, FloatRegister vtmp1,
-                           FloatRegister vtmp2, FloatRegister vtmp3);
+                           FloatRegister tmp1Reg, FloatRegister tmp2Reg,
+                           FloatRegister tmp3Reg, FloatRegister tmp4Reg,
+                           Register result);
 
   void encode_iso_array(Register src, Register dst,
-                        Register len, Register res, bool ascii,
-                        FloatRegister vtmp0, FloatRegister vtmp1,
-                        FloatRegister vtmp2, FloatRegister vtmp3);
-
+                        Register len, Register result,
+                        FloatRegister Vtmp1, FloatRegister Vtmp2,
+                        FloatRegister Vtmp3, FloatRegister Vtmp4);
   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,

src/hotspot/cpu/aarch64/matcher_aarch64.hpp

@@ -156,6 +156,6 @@
   }
 
   // Implements a variant of EncodeISOArrayNode that encode ASCII only
-  static const bool supports_encode_ascii_array = true;
+  static const bool supports_encode_ascii_array = false;
 
 #endif // CPU_AARCH64_MATCHER_AARCH64_HPP

src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp

@@ -39,9 +39,6 @@
 #ifdef COMPILER1
 #include "c1/c1_Runtime1.hpp"
 #endif
-#if INCLUDE_JVMCI
-#include "jvmci/jvmciEnv.hpp"
-#endif
 
 void NativeCall::verify() {
   assert(NativeCall::is_call_at((address)this), "unexpected code at call site");
@@ -527,26 +524,23 @@ void NativeCallTrampolineStub::set_destination(address new_destination) {
   OrderAccess::release();
 }
 
-#if INCLUDE_JVMCI
 // Generate a trampoline for a branch to dest.  If there's no need for a
 // trampoline, simply patch the call directly to dest.
-void NativeCall::trampoline_jump(CodeBuffer &cbuf, address dest, JVMCI_TRAPS) {
+address NativeCall::trampoline_jump(CodeBuffer &cbuf, address dest) {
   MacroAssembler a(&cbuf);
+  address stub = NULL;
 
-  if (!a.far_branches()) {
-    // If not using far branches, patch this call directly to dest.
-    set_destination(dest);
-  } else if (!is_NativeCallTrampolineStub_at(instruction_address() + displacement())) {
-    // If we want far branches and there isn't a trampoline stub, emit one.
-    address stub = a.emit_trampoline_stub(instruction_address() - cbuf.insts()->start(), dest);
-    if (stub == nullptr) {
-      JVMCI_ERROR("could not emit trampoline stub - code cache is full");
-    }
-    // The relocation created while emitting the stub will ensure this
-    // call instruction is subsequently patched to call the stub.
-  } else {
-    // Not sure how this can be happen but be defensive
-    JVMCI_ERROR("single-use stub should not exist");
+  if (a.far_branches()
+      && ! is_NativeCallTrampolineStub_at(instruction_address() + displacement())) {
+    stub = a.emit_trampoline_stub(instruction_address() - cbuf.insts()->start(), dest);
   }
+
+  if (stub == NULL) {
+    // If we generated no stub, patch this call directly to dest.
+    // This will happen if we don't need far branches or if there
+    // already was a trampoline.
+    set_destination(dest);
+  }
+
+  return stub;
 }
-#endif

src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp

@@ -29,11 +29,6 @@
 #include "asm/assembler.hpp"
 #include "runtime/icache.hpp"
 #include "runtime/os.hpp"
-#include "runtime/os.hpp"
-#if INCLUDE_JVMCI
-#include "jvmci/jvmciExceptions.hpp"
-#endif
-
 
 // We have interfaces for the following instructions:
 // - NativeInstruction
@@ -256,9 +251,7 @@ public:
   void set_destination_mt_safe(address dest, bool assert_lock = true);
 
   address get_trampoline();
-#if INCLUDE_JVMCI
-  void trampoline_jump(CodeBuffer &cbuf, address dest, JVMCI_TRAPS);
-#endif
+  address trampoline_jump(CodeBuffer &cbuf, address dest);
 };
 
 inline NativeCall* nativeCall_at(address address) {

src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp

@@ -2359,9 +2359,10 @@ void SharedRuntime::generate_deopt_blob() {
 
   Label retaddr;
   __ set_last_Java_frame(sp, noreg, retaddr, rscratch1);
-#ifdef ASSERT
+#ifdef ASSERT0
   { Label L;
-    __ ldr(rscratch1, Address(rthread, JavaThread::last_Java_fp_offset()));
+    __ ldr(rscratch1, Address(rthread,
+                              JavaThread::last_Java_fp_offset()));
     __ cbz(rscratch1, L);
     __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
     __ bind(L);

src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp

@@ -2964,22 +2964,6 @@ class StubGenerator: public StubCodeGenerator {
     return start;
   }
 
-  // Big-endian 128-bit + 64-bit -> 128-bit addition.
-  // Inputs: 128-bits. in is preserved.
-  // The least-significant 64-bit word is in the upper dword of the vector
-  // inc (the 64-bit increment) is preserved. Its lower dword must be zero
-  // Output: result
-  void be_add_128_64(FloatRegister result, FloatRegister in,
-               FloatRegister inc, FloatRegister tmp) {
-    assert_different_registers(result, tmp, inc);
-
-    __ addv(result, __ T2D, in, inc);      // Add inc to the least-significant dword of input
-    __ cmhi(tmp, __ T2D, inc, result);     // Check for result overflowing
-    __ ins(tmp, __ D, tmp, 0, 1);          // Move LSD of comparison result to MSD
-    __ ins(tmp, __ D, inc, 1, 0);          // Move 0 to LSD of comparison result
-    __ subv(result, __ T2D, result, tmp);  // Subtract -1 from MSD if there was an overflow
-  }
-
   // CTR AES crypt.
   // Arguments:
   //
@@ -3089,16 +3073,13 @@ class StubGenerator: public StubCodeGenerator {
       // Setup the counter
       __ movi(v4, __ T4S, 0);
       __ movi(v5, __ T4S, 1);
-      __ ins(v4, __ S, v5, 2, 2); // v4 contains { 0, 1 }
+      __ ins(v4, __ S, v5, 3, 3); // v4 contains { 0, 0, 0, 1 }
 
-      // 128-bit big-endian increment
-      __ ld1(v0, __ T16B, counter);
-      __ rev64(v16, __ T16B, v0);
-      be_add_128_64(v16, v16, v4, /*tmp*/v5);
-      __ rev64(v16, __ T16B, v16);
-      __ st1(v16, __ T16B, counter);
-      // Previous counter value is in v0
-      // v4 contains { 0, 1 }
+      __ ld1(v0, __ T16B, counter); // Load the counter into v0
+      __ rev32(v16, __ T16B, v0);
+      __ addv(v16, __ T4S, v16, v4);
+      __ rev32(v16, __ T16B, v16);
+      __ st1(v16, __ T16B, counter); // Save the incremented counter back
 
       {
         // We have fewer than bulk_width blocks of data left. Encrypt
@@ -3130,9 +3111,9 @@ class StubGenerator: public StubCodeGenerator {
 
         // Increment the counter, store it back
         __ orr(v0, __ T16B, v16, v16);
-        __ rev64(v16, __ T16B, v16);
-        be_add_128_64(v16, v16, v4, /*tmp*/v5);
-        __ rev64(v16, __ T16B, v16);
+        __ rev32(v16, __ T16B, v16);
+        __ addv(v16, __ T4S, v16, v4);
+        __ rev32(v16, __ T16B, v16);
         __ st1(v16, __ T16B, counter); // Save the incremented counter back
 
         __ b(inner_loop);
@@ -3180,7 +3161,7 @@ class StubGenerator: public StubCodeGenerator {
     // Keys should already be loaded into the correct registers
 
     __ ld1(v0, __ T16B, counter); // v0 contains the first counter
-    __ rev64(v16, __ T16B, v0); // v16 contains byte-reversed counter
+    __ rev32(v16, __ T16B, v0); // v16 contains byte-reversed counter
 
     // AES/CTR loop
     {
@@ -3190,11 +3171,11 @@ class StubGenerator: public StubCodeGenerator {
       // Setup the counters
       __ movi(v8, __ T4S, 0);
       __ movi(v9, __ T4S, 1);
-      __ ins(v8, __ S, v9, 2, 2); // v8 contains { 0, 1 }
+      __ ins(v8, __ S, v9, 3, 3); // v8 contains { 0, 0, 0, 1 }
 
       for (FloatRegister f = v0; f < v0 + bulk_width; f++) {
-        __ rev64(f, __ T16B, v16);
-        be_add_128_64(v16, v16, v8, /*tmp*/v9);
+        __ rev32(f, __ T16B, v16);
+        __ addv(v16, __ T4S, v16, v8);
       }
 
       __ ld1(v8, v9, v10, v11, __ T16B, __ post(in, 4 * 16));
@@ -3222,7 +3203,7 @@ class StubGenerator: public StubCodeGenerator {
     }
 
     // Save the counter back where it goes
-    __ rev64(v16, __ T16B, v16);
+    __ rev32(v16, __ T16B, v16);
     __ st1(v16, __ T16B, counter);
 
     __ pop(saved_regs, sp);
@@ -4021,6 +4002,46 @@ class StubGenerator: public StubCodeGenerator {
     return start;
   }
 
+  // Safefetch stubs.
+  void generate_safefetch(const char* name, int size, address* entry,
+                          address* fault_pc, address* continuation_pc) {
+    // safefetch signatures:
+    //   int      SafeFetch32(int*      adr, int      errValue);
+    //   intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue);
+    //
+    // arguments:
+    //   c_rarg0 = adr
+    //   c_rarg1 = errValue
+    //
+    // result:
+    //   PPC_RET  = *adr or errValue
+
+    StubCodeMark mark(this, "StubRoutines", name);
+
+    // Entry point, pc or function descriptor.
+    *entry = __ pc();
+
+    // Load *adr into c_rarg1, may fault.
+    *fault_pc = __ pc();
+    switch (size) {
+      case 4:
+        // int32_t
+        __ ldrw(c_rarg1, Address(c_rarg0, 0));
+        break;
+      case 8:
+        // int64_t
+        __ ldr(c_rarg1, Address(c_rarg0, 0));
+        break;
+      default:
+        ShouldNotReachHere();
+    }
+
+    // return errValue or *adr
+    *continuation_pc = __ pc();
+    __ mov(r0, c_rarg1);
+    __ ret(lr);
+  }
+
   /**
    *  Arguments:
    *
@@ -6460,16 +6481,10 @@ class StubGenerator: public StubCodeGenerator {
     __ ret(lr);
   }
 
-  void gen_ldadd_entry(Assembler::operand_size size, atomic_memory_order order) {
+  void gen_ldaddal_entry(Assembler::operand_size size) {
     Register prev = r2, addr = c_rarg0, incr = c_rarg1;
-    // If not relaxed, then default to conservative.  Relaxed is the only
-    // case we use enough to be worth specializing.
-    if (order == memory_order_relaxed) {
-      __ ldadd(size, incr, prev, addr);
-    } else {
-      __ ldaddal(size, incr, prev, addr);
-      __ membar(Assembler::StoreStore|Assembler::StoreLoad);
-    }
+    __ ldaddal(size, incr, prev, addr);
+    __ membar(Assembler::StoreStore|Assembler::StoreLoad);
     if (size == Assembler::xword) {
       __ mov(r0, prev);
     } else {
@@ -6499,21 +6514,12 @@ class StubGenerator: public StubCodeGenerator {
     StubCodeMark mark(this, "StubRoutines", "atomic entry points");
     address first_entry = __ pc();
 
-    // ADD, memory_order_conservative
+    // All memory_order_conservative
     AtomicStubMark mark_fetch_add_4(_masm, &aarch64_atomic_fetch_add_4_impl);
-    gen_ldadd_entry(Assembler::word, memory_order_conservative);
+    gen_ldaddal_entry(Assembler::word);
     AtomicStubMark mark_fetch_add_8(_masm, &aarch64_atomic_fetch_add_8_impl);
-    gen_ldadd_entry(Assembler::xword, memory_order_conservative);
+    gen_ldaddal_entry(Assembler::xword);
 
-    // ADD, memory_order_relaxed
-    AtomicStubMark mark_fetch_add_4_relaxed
-      (_masm, &aarch64_atomic_fetch_add_4_relaxed_impl);
-    gen_ldadd_entry(MacroAssembler::word, memory_order_relaxed);
-    AtomicStubMark mark_fetch_add_8_relaxed
-      (_masm, &aarch64_atomic_fetch_add_8_relaxed_impl);
-    gen_ldadd_entry(MacroAssembler::xword, memory_order_relaxed);
-
-    // XCHG, memory_order_conservative
     AtomicStubMark mark_xchg_4(_masm, &aarch64_atomic_xchg_4_impl);
     gen_swpal_entry(Assembler::word);
     AtomicStubMark mark_xchg_8_impl(_masm, &aarch64_atomic_xchg_8_impl);
@@ -7538,6 +7544,14 @@ class StubGenerator: public StubCodeGenerator {
     if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dcos)) {
       StubRoutines::_dcos = generate_dsin_dcos(/* isCos = */ true);
     }
+
+    // Safefetch stubs.
+    generate_safefetch("SafeFetch32", sizeof(int),     &StubRoutines::_safefetch32_entry,
+                                                       &StubRoutines::_safefetch32_fault_pc,
+                                                       &StubRoutines::_safefetch32_continuation_pc);
+    generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry,
+                                                       &StubRoutines::_safefetchN_fault_pc,
+                                                       &StubRoutines::_safefetchN_continuation_pc);
   }
 
   void generate_all() {
@@ -7716,8 +7730,6 @@ void StubGenerator_generate(CodeBuffer* code, bool all) {
 
 DEFAULT_ATOMIC_OP(fetch_add, 4, )
 DEFAULT_ATOMIC_OP(fetch_add, 8, )
-DEFAULT_ATOMIC_OP(fetch_add, 4, _relaxed)
-DEFAULT_ATOMIC_OP(fetch_add, 8, _relaxed)
 DEFAULT_ATOMIC_OP(xchg, 4, )
 DEFAULT_ATOMIC_OP(xchg, 8, )
 DEFAULT_ATOMIC_OP(cmpxchg, 1, )

src/hotspot/cpu/aarch64/vm_version_aarch64.cpp

@@ -493,52 +493,36 @@ void VM_Version::initialize() {
   UNSUPPORTED_OPTION(CriticalJNINatives);
 }
 
+void VM_Version::check_virtualizations() {
 #if defined(LINUX)
-static bool check_info_file(const char* fpath,
-                            const char* virt1, VirtualizationType vt1,
-                            const char* virt2, VirtualizationType vt2) {
+  const char* info_file = "/sys/devices/virtual/dmi/id/product_name";
+  // check for various strings in the dmi data indicating virtualizations
   char line[500];
-  FILE* fp = os::fopen(fpath, "r");
+  FILE* fp = os::fopen(info_file, "r");
   if (fp == nullptr) {
-    return false;
+    return;
   }
   while (fgets(line, sizeof(line), fp) != nullptr) {
-    if (strcasestr(line, virt1) != 0) {
-      Abstract_VM_Version::_detected_virtualization = vt1;
-      fclose(fp);
-      return true;
+    if (strcasestr(line, "KVM") != 0) {
+      Abstract_VM_Version::_detected_virtualization = KVM;
+      break;
     }
-    if (virt2 != NULL && strcasestr(line, virt2) != 0) {
-      Abstract_VM_Version::_detected_virtualization = vt2;
-      fclose(fp);
-      return true;
+    if (strcasestr(line, "VMware") != 0) {
+      Abstract_VM_Version::_detected_virtualization = VMWare;
+      break;
     }
   }
   fclose(fp);
-  return false;
-}
-#endif
-
-void VM_Version::check_virtualizations() {
-#if defined(LINUX)
-  const char* pname_file = "/sys/devices/virtual/dmi/id/product_name";
-  const char* tname_file = "/sys/hypervisor/type";
-  if (check_info_file(pname_file, "KVM", KVM, "VMWare", VMWare)) {
-    return;
-  }
-  check_info_file(tname_file, "Xen", XenPVHVM, NULL, NoDetectedVirtualization);
 #endif
 }
 
 void VM_Version::print_platform_virtualization_info(outputStream* st) {
 #if defined(LINUX)
-  VirtualizationType vrt = VM_Version::get_detected_virtualization();
-  if (vrt == KVM) {
-    st->print_cr("KVM virtualization detected");
-  } else if (vrt == VMWare) {
-    st->print_cr("VMWare virtualization detected");
-  } else if (vrt == XenPVHVM) {
-    st->print_cr("Xen virtualization detected");
-  }
+    VirtualizationType vrt = VM_Version::get_detected_virtualization();
+    if (vrt == KVM) {
+      st->print_cr("KVM virtualization detected");
+    } else if (vrt == VMWare) {
+      st->print_cr("VMWare virtualization detected");
+    }
 #endif
 }

src/hotspot/cpu/arm/arm.ad

@@ -4511,7 +4511,6 @@ instruct storeF( memoryF mem, regF src) %{
 // pattern-match out unnecessary membars
 instruct membar_storestore() %{
   match(MemBarStoreStore);
-  match(StoreStoreFence);
   ins_cost(4*MEMORY_REF_COST);
 
   size(4);

src/hotspot/cpu/arm/c2_MacroAssembler_arm.cpp

@@ -160,7 +160,7 @@ void C2_MacroAssembler::fast_unlock(Register Roop, Register Rbox, Register Rscra
   // Restore the object header
   bool allow_fallthrough_on_failure = true;
   bool one_shot = true;
-  cas_for_lock_release(Rbox, Rmark, Roop, Rscratch, done, allow_fallthrough_on_failure, one_shot);
+  cas_for_lock_release(Rmark, Rbox, Roop, Rscratch, done, allow_fallthrough_on_failure, one_shot);
 
   bind(done);
 }

src/hotspot/cpu/arm/stubGenerator_arm.cpp

@@ -2837,6 +2837,46 @@ class StubGenerator: public StubCodeGenerator {
     return start;
   }
 
+  // Safefetch stubs.
+  void generate_safefetch(const char* name, int size, address* entry, address* fault_pc, address* continuation_pc) {
+    // safefetch signatures:
+    //   int      SafeFetch32(int*      adr, int      errValue);
+    //   intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue);
+    //
+    // arguments:
+    //   R0 = adr
+    //   R1 = errValue
+    //
+    // result:
+    //   R0  = *adr or errValue
+
+    StubCodeMark mark(this, "StubRoutines", name);
+
+    // Entry point, pc or function descriptor.
+    *entry = __ pc();
+
+    // Load *adr into c_rarg2, may fault.
+    *fault_pc = __ pc();
+
+    switch (size) {
+      case 4: // int32_t
+        __ ldr_s32(R1, Address(R0));
+        break;
+
+      case 8: // int64_t
+        Unimplemented();
+        break;
+
+      default:
+        ShouldNotReachHere();
+    }
+
+    // return errValue or *adr
+    *continuation_pc = __ pc();
+    __ mov(R0, R1);
+    __ ret();
+  }
+
   void generate_arraycopy_stubs() {
 
     // Note:  the disjoint stubs must be generated first, some of
@@ -2989,9 +3029,16 @@ class StubGenerator: public StubCodeGenerator {
     StubRoutines::_atomic_load_long_entry = generate_atomic_load_long();
     StubRoutines::_atomic_store_long_entry = generate_atomic_store_long();
 
+    // Safefetch stubs.
+    generate_safefetch("SafeFetch32", sizeof(int), &StubRoutines::_safefetch32_entry,
+                                                   &StubRoutines::_safefetch32_fault_pc,
+                                                   &StubRoutines::_safefetch32_continuation_pc);
+    assert (sizeof(int) == wordSize, "32-bit architecture");
+    StubRoutines::_safefetchN_entry           = StubRoutines::_safefetch32_entry;
+    StubRoutines::_safefetchN_fault_pc        = StubRoutines::_safefetch32_fault_pc;
+    StubRoutines::_safefetchN_continuation_pc = StubRoutines::_safefetch32_continuation_pc;
   }
 
-
   void generate_all() {
     // Generates all stubs and initializes the entry points
 

src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp

@@ -828,6 +828,7 @@ int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType typ
           } else {
             __ ld(to_reg->as_register(), offset, base);
           }
+          __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
           break;
         }
       case T_FLOAT:  __ lfs(to_reg->as_float_reg(), offset, base); break;
@@ -858,6 +859,7 @@ int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType
         } else {
           __ ldx(to_reg->as_register(), base, disp);
         }
+        __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
         break;
       }
     case T_FLOAT:  __ lfsx(to_reg->as_float_reg() , base, disp); break;

src/hotspot/cpu/ppc/ppc.ad

@@ -7152,7 +7152,6 @@ instruct membar_release() %{
 
 instruct membar_storestore() %{
   match(MemBarStoreStore);
-  match(StoreStoreFence);
   ins_cost(4*MEMORY_REF_COST);
 
   format %{ "MEMBAR-store-store" %}

src/hotspot/cpu/ppc/stubGenerator_ppc.cpp

@@ -3159,6 +3159,45 @@ class StubGenerator: public StubCodeGenerator {
 #endif
   }
 
+  // Safefetch stubs.
+  void generate_safefetch(const char* name, int size, address* entry, address* fault_pc, address* continuation_pc) {
+    // safefetch signatures:
+    //   int      SafeFetch32(int*      adr, int      errValue);
+    //   intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue);
+    //
+    // arguments:
+    //   R3_ARG1 = adr
+    //   R4_ARG2 = errValue
+    //
+    // result:
+    //   R3_RET  = *adr or errValue
+
+    StubCodeMark mark(this, "StubRoutines", name);
+
+    // Entry point, pc or function descriptor.
+    *entry = __ function_entry();
+
+    // Load *adr into R4_ARG2, may fault.
+    *fault_pc = __ pc();
+    switch (size) {
+      case 4:
+        // int32_t, signed extended
+        __ lwa(R4_ARG2, 0, R3_ARG1);
+        break;
+      case 8:
+        // int64_t
+        __ ld(R4_ARG2, 0, R3_ARG1);
+        break;
+      default:
+        ShouldNotReachHere();
+    }
+
+    // return errValue or *adr
+    *continuation_pc = __ pc();
+    __ mr(R3_RET, R4_ARG2);
+    __ blr();
+  }
+
   // Stub for BigInteger::multiplyToLen()
   //
   //  Arguments:
@@ -4495,6 +4534,14 @@ class StubGenerator: public StubCodeGenerator {
       StubRoutines::_crc32c_table_addr = StubRoutines::ppc::generate_crc_constants(REVERSE_CRC32C_POLY);
       StubRoutines::_updateBytesCRC32C = generate_CRC32_updateBytes(true);
     }
+
+    // Safefetch stubs.
+    generate_safefetch("SafeFetch32", sizeof(int),     &StubRoutines::_safefetch32_entry,
+                                                       &StubRoutines::_safefetch32_fault_pc,
+                                                       &StubRoutines::_safefetch32_continuation_pc);
+    generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry,
+                                                       &StubRoutines::_safefetchN_fault_pc,
+                                                       &StubRoutines::_safefetchN_continuation_pc);
   }
 
   void generate_all() {

src/hotspot/cpu/riscv/abstractInterpreter_riscv.cpp

@@ -1,177 +0,0 @@
-/*
- * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "interpreter/interpreter.hpp"
-#include "oops/constMethod.hpp"
-#include "oops/klass.inline.hpp"
-#include "oops/method.hpp"
-#include "runtime/frame.inline.hpp"
-#include "utilities/align.hpp"
-#include "utilities/debug.hpp"
-#include "utilities/macros.hpp"
-
-int AbstractInterpreter::BasicType_as_index(BasicType type) {
-  int i = 0;
-  switch (type) {
-    case T_BOOLEAN: i = 0; break;
-    case T_CHAR   : i = 1; break;
-    case T_BYTE   : i = 2; break;
-    case T_SHORT  : i = 3; break;
-    case T_INT    : i = 4; break;
-    case T_LONG   : i = 5; break;
-    case T_VOID   : i = 6; break;
-    case T_FLOAT  : i = 7; break;
-    case T_DOUBLE : i = 8; break;
-    case T_OBJECT : i = 9; break;
-    case T_ARRAY  : i = 9; break;
-    default       : ShouldNotReachHere();
-  }
-  assert(0 <= i && i < AbstractInterpreter::number_of_result_handlers,
-         "index out of bounds");
-  return i;
-}
-
-// How much stack a method activation needs in words.
-int AbstractInterpreter::size_top_interpreter_activation(Method* method) {
-  const int entry_size = frame::interpreter_frame_monitor_size();
-
-  // total overhead size: entry_size + (saved fp thru expr stack
-  // bottom).  be sure to change this if you add/subtract anything
-  // to/from the overhead area
-  const int overhead_size =
-    -(frame::interpreter_frame_initial_sp_offset) + entry_size;
-
-  const int stub_code = frame::entry_frame_after_call_words;
-  assert_cond(method != NULL);
-  const int method_stack = (method->max_locals() + method->max_stack()) *
-                           Interpreter::stackElementWords;
-  return (overhead_size + method_stack + stub_code);
-}
-
-// asm based interpreter deoptimization helpers
-int AbstractInterpreter::size_activation(int max_stack,
-                                         int temps,
-                                         int extra_args,
-                                         int monitors,
-                                         int callee_params,
-                                         int callee_locals,
-                                         bool is_top_frame) {
-  // Note: This calculation must exactly parallel the frame setup
-  // in TemplateInterpreterGenerator::generate_method_entry.
-
-  // fixed size of an interpreter frame:
-  int overhead = frame::sender_sp_offset -
-                 frame::interpreter_frame_initial_sp_offset;
-  // Our locals were accounted for by the caller (or last_frame_adjust
-  // on the transistion) Since the callee parameters already account
-  // for the callee's params we only need to account for the extra
-  // locals.
-  int size = overhead +
-             (callee_locals - callee_params) +
-             monitors * frame::interpreter_frame_monitor_size() +
-             // On the top frame, at all times SP <= ESP, and SP is
-             // 16-aligned.  We ensure this by adjusting SP on method
-             // entry and re-entry to allow room for the maximum size of
-             // the expression stack.  When we call another method we bump
-             // SP so that no stack space is wasted.  So, only on the top
-             // frame do we need to allow max_stack words.
-             (is_top_frame ? max_stack : temps + extra_args);
-
-  // On riscv we always keep the stack pointer 16-aligned, so we
-  // must round up here.
-  size = align_up(size, 2);
-
-  return size;
-}
-
-void AbstractInterpreter::layout_activation(Method* method,
-                                            int tempcount,
-                                            int popframe_extra_args,
-                                            int moncount,
-                                            int caller_actual_parameters,
-                                            int callee_param_count,
-                                            int callee_locals,
-                                            frame* caller,
-                                            frame* interpreter_frame,
-                                            bool is_top_frame,
-                                            bool is_bottom_frame) {
-  // The frame interpreter_frame is guaranteed to be the right size,
-  // as determined by a previous call to the size_activation() method.
-  // It is also guaranteed to be walkable even though it is in a
-  // skeletal state
-  assert_cond(method != NULL && caller != NULL && interpreter_frame != NULL);
-  int max_locals = method->max_locals() * Interpreter::stackElementWords;
-  int extra_locals = (method->max_locals() - method->size_of_parameters()) *
-    Interpreter::stackElementWords;
-
-#ifdef ASSERT
-  assert(caller->sp() == interpreter_frame->sender_sp(), "Frame not properly walkable");
-#endif
-
-  interpreter_frame->interpreter_frame_set_method(method);
-  // NOTE the difference in using sender_sp and interpreter_frame_sender_sp
-  // interpreter_frame_sender_sp is the original sp of the caller (the unextended_sp)
-  // and sender_sp is fp
-  intptr_t* locals = NULL;
-  if (caller->is_interpreted_frame()) {
-    locals = caller->interpreter_frame_last_sp() + caller_actual_parameters - 1;
-  } else {
-    locals = interpreter_frame->sender_sp() + max_locals - 1;
-  }
-
-#ifdef ASSERT
-  if (caller->is_interpreted_frame()) {
-    assert(locals < caller->fp() + frame::interpreter_frame_initial_sp_offset, "bad placement");
-  }
-#endif
-
-  interpreter_frame->interpreter_frame_set_locals(locals);
-  BasicObjectLock* montop = interpreter_frame->interpreter_frame_monitor_begin();
-  BasicObjectLock* monbot = montop - moncount;
-  interpreter_frame->interpreter_frame_set_monitor_end(monbot);
-
-  // Set last_sp
-  intptr_t* last_sp = (intptr_t*) monbot -
-    tempcount*Interpreter::stackElementWords -
-    popframe_extra_args;
-  interpreter_frame->interpreter_frame_set_last_sp(last_sp);
-
-  // All frames but the initial (oldest) interpreter frame we fill in have
-  // a value for sender_sp that allows walking the stack but isn't
-  // truly correct. Correct the value here.
-  if (extra_locals != 0 &&
-      interpreter_frame->sender_sp() ==
-      interpreter_frame->interpreter_frame_sender_sp()) {
-    interpreter_frame->set_interpreter_frame_sender_sp(caller->sp() +
-                                                       extra_locals);
-  }
-
-  *interpreter_frame->interpreter_frame_cache_addr() =
-    method->constants()->cache();
-  *interpreter_frame->interpreter_frame_mirror_addr() =
-    method->method_holder()->java_mirror();
-}

src/hotspot/cpu/riscv/assembler_riscv.cpp

@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include <stdio.h>
-#include <sys/types.h>
-
-#include "precompiled.hpp"
-#include "asm/assembler.hpp"
-#include "asm/assembler.inline.hpp"
-#include "compiler/disassembler.hpp"
-#include "interpreter/interpreter.hpp"
-#include "memory/resourceArea.hpp"
-#include "runtime/interfaceSupport.inline.hpp"
-#include "runtime/sharedRuntime.hpp"
-
-int AbstractAssembler::code_fill_byte() {
-  return 0;
-}
-
-Address::Address(address target, relocInfo::relocType rtype) : _base(noreg), _offset(0), _mode(literal) {
-  _target = target;
-  switch (rtype) {
-    case relocInfo::oop_type:
-    case relocInfo::metadata_type:
-      // Oops are a special case. Normally they would be their own section
-      // but in cases like icBuffer they are literals in the code stream that
-      // we don't have a section for. We use none so that we get a literal address
-      // which is always patchable.
-      break;
-    case relocInfo::external_word_type:
-      _rspec = external_word_Relocation::spec(target);
-      break;
-    case relocInfo::internal_word_type:
-      _rspec = internal_word_Relocation::spec(target);
-      break;
-    case relocInfo::opt_virtual_call_type:
-      _rspec = opt_virtual_call_Relocation::spec();
-      break;
-    case relocInfo::static_call_type:
-      _rspec = static_call_Relocation::spec();
-      break;
-    case relocInfo::runtime_call_type:
-      _rspec = runtime_call_Relocation::spec();
-      break;
-    case relocInfo::poll_type:
-    case relocInfo::poll_return_type:
-      _rspec = Relocation::spec_simple(rtype);
-      break;
-    case relocInfo::none:
-      _rspec = RelocationHolder::none;
-      break;
-    default:
-      ShouldNotReachHere();
-  }
-}

src/hotspot/cpu/riscv/assembler_riscv.inline.hpp

@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_ASSEMBLER_RISCV_INLINE_HPP
-#define CPU_RISCV_ASSEMBLER_RISCV_INLINE_HPP
-
-#include "asm/assembler.inline.hpp"
-#include "asm/codeBuffer.hpp"
-#include "code/codeCache.hpp"
-
-inline bool Assembler::is_simm5(int64_t x) { return is_simm(x, 5); }
-inline bool Assembler::is_simm6(int64_t x) { return is_simm(x, 6); }
-inline bool Assembler::is_simm12(int64_t x) { return is_simm(x, 12); }
-inline bool Assembler::is_simm13(int64_t x) { return is_simm(x, 13); }
-inline bool Assembler::is_simm18(int64_t x) { return is_simm(x, 18); }
-inline bool Assembler::is_simm21(int64_t x) { return is_simm(x, 21); }
-
-inline bool Assembler::is_uimm3(uint64_t x) { return is_uimm(x, 3); }
-inline bool Assembler::is_uimm5(uint64_t x) { return is_uimm(x, 5); }
-inline bool Assembler::is_uimm6(uint64_t x) { return is_uimm(x, 6); }
-inline bool Assembler::is_uimm7(uint64_t x) { return is_uimm(x, 7); }
-inline bool Assembler::is_uimm8(uint64_t x) { return is_uimm(x, 8); }
-inline bool Assembler::is_uimm9(uint64_t x) { return is_uimm(x, 9); }
-inline bool Assembler::is_uimm10(uint64_t x) { return is_uimm(x, 10); }
-
-#endif // CPU_RISCV_ASSEMBLER_RISCV_INLINE_HPP

src/hotspot/cpu/riscv/bytes_riscv.hpp

@@ -1,169 +0,0 @@
-/*
- * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_BYTES_RISCV_HPP
-#define CPU_RISCV_BYTES_RISCV_HPP
-
-#include "memory/allStatic.hpp"
-
-class Bytes: AllStatic {
- public:
-  // Efficient reading and writing of unaligned unsigned data in platform-specific byte ordering
-  // RISCV needs to check for alignment.
-
-  // Forward declarations of the compiler-dependent implementation
-  static inline u2 swap_u2(u2 x);
-  static inline u4 swap_u4(u4 x);
-  static inline u8 swap_u8(u8 x);
-
-  static inline u2 get_native_u2(address p) {
-    if ((intptr_t(p) & 1) == 0) {
-      return *(u2*)p;
-    } else {
-      return ((u2)(p[1]) << 8) |
-             ((u2)(p[0]));
-    }
-  }
-
-  static inline u4 get_native_u4(address p) {
-    switch (intptr_t(p) & 3) {
-      case 0:
-        return *(u4*)p;
-
-      case 2:
-        return ((u4)(((u2*)p)[1]) << 16) |
-               ((u4)(((u2*)p)[0]));
-
-      default:
-        return ((u4)(p[3]) << 24) |
-               ((u4)(p[2]) << 16) |
-               ((u4)(p[1]) <<  8) |
-               ((u4)(p[0]));
-    }
-  }
-
-  static inline u8 get_native_u8(address p) {
-    switch (intptr_t(p) & 7) {
-      case 0:
-        return *(u8*)p;
-
-      case 4:
-        return ((u8)(((u4*)p)[1]) << 32) |
-               ((u8)(((u4*)p)[0]));
-
-      case 2:
-      case 6:
-        return ((u8)(((u2*)p)[3]) << 48) |
-               ((u8)(((u2*)p)[2]) << 32) |
-               ((u8)(((u2*)p)[1]) << 16) |
-               ((u8)(((u2*)p)[0]));
-
-      default:
-        return ((u8)(p[7]) << 56) |
-               ((u8)(p[6]) << 48) |
-               ((u8)(p[5]) << 40) |
-               ((u8)(p[4]) << 32) |
-               ((u8)(p[3]) << 24) |
-               ((u8)(p[2]) << 16) |
-               ((u8)(p[1]) <<  8) |
-               ((u8)(p[0]));
-    }
-  }
-
-  static inline void put_native_u2(address p, u2 x) {
-    if ((intptr_t(p) & 1) == 0) {
-      *(u2*)p = x;
-    } else {
-      p[1] = x >> 8;
-      p[0] = x;
-    }
-  }
-
-  static inline void put_native_u4(address p, u4 x) {
-    switch (intptr_t(p) & 3) {
-      case 0:
-        *(u4*)p = x;
-        break;
-
-      case 2:
-        ((u2*)p)[1] = x >> 16;
-        ((u2*)p)[0] = x;
-        break;
-
-      default:
-        ((u1*)p)[3] = x >> 24;
-        ((u1*)p)[2] = x >> 16;
-        ((u1*)p)[1] = x >>  8;
-        ((u1*)p)[0] = x;
-        break;
-    }
-  }
-
-  static inline void put_native_u8(address p, u8 x) {
-    switch (intptr_t(p) & 7) {
-      case 0:
-        *(u8*)p = x;
-        break;
-
-      case 4:
-        ((u4*)p)[1] = x >> 32;
-        ((u4*)p)[0] = x;
-        break;
-
-      case 2:
-      case 6:
-        ((u2*)p)[3] = x >> 48;
-        ((u2*)p)[2] = x >> 32;
-        ((u2*)p)[1] = x >> 16;
-        ((u2*)p)[0] = x;
-        break;
-
-      default:
-        ((u1*)p)[7] = x >> 56;
-        ((u1*)p)[6] = x >> 48;
-        ((u1*)p)[5] = x >> 40;
-        ((u1*)p)[4] = x >> 32;
-        ((u1*)p)[3] = x >> 24;
-        ((u1*)p)[2] = x >> 16;
-        ((u1*)p)[1] = x >>  8;
-        ((u1*)p)[0] = x;
-        break;
-    }
-  }
-
-  // Efficient reading and writing of unaligned unsigned data in Java byte ordering (i.e. big-endian ordering)
-  static inline u2 get_Java_u2(address p) { return swap_u2(get_native_u2(p)); }
-  static inline u4 get_Java_u4(address p) { return swap_u4(get_native_u4(p)); }
-  static inline u8 get_Java_u8(address p) { return swap_u8(get_native_u8(p)); }
-
-  static inline void put_Java_u2(address p, u2 x) { put_native_u2(p, swap_u2(x)); }
-  static inline void put_Java_u4(address p, u4 x) { put_native_u4(p, swap_u4(x)); }
-  static inline void put_Java_u8(address p, u8 x) { put_native_u8(p, swap_u8(x)); }
-};
-
-#include OS_CPU_HEADER(bytes)
-
-#endif // CPU_RISCV_BYTES_RISCV_HPP

src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp

@@ -1,357 +0,0 @@
-/*
- * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "asm/macroAssembler.inline.hpp"
-#include "c1/c1_CodeStubs.hpp"
-#include "c1/c1_FrameMap.hpp"
-#include "c1/c1_LIRAssembler.hpp"
-#include "c1/c1_MacroAssembler.hpp"
-#include "c1/c1_Runtime1.hpp"
-#include "classfile/javaClasses.hpp"
-#include "nativeInst_riscv.hpp"
-#include "runtime/sharedRuntime.hpp"
-#include "vmreg_riscv.inline.hpp"
-
-
-#define __ ce->masm()->
-
-void C1SafepointPollStub::emit_code(LIR_Assembler* ce) {
-  __ bind(_entry);
-  InternalAddress safepoint_pc(__ pc() - __ offset() + safepoint_offset());
-  __ relocate(safepoint_pc.rspec(), [&] {
-    __ la(t0, safepoint_pc.target());
-  });
-  __ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset()));
-
-  assert(SharedRuntime::polling_page_return_handler_blob() != NULL,
-         "polling page return stub not created yet");
-  address stub = SharedRuntime::polling_page_return_handler_blob()->entry_point();
-
-  __ far_jump(RuntimeAddress(stub));
-}
-
-void CounterOverflowStub::emit_code(LIR_Assembler* ce) {
-  __ bind(_entry);
-  Metadata *m = _method->as_constant_ptr()->as_metadata();
-  __ mov_metadata(t0, m);
-  ce->store_parameter(t0, 1);
-  ce->store_parameter(_bci, 0);
-  __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::counter_overflow_id)));
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-  __ j(_continuation);
-}
-
-RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index, LIR_Opr array)
-  : _index(index), _array(array), _throw_index_out_of_bounds_exception(false) {
-  assert(info != NULL, "must have info");
-  _info = new CodeEmitInfo(info);
-}
-
-RangeCheckStub::RangeCheckStub(CodeEmitInfo* info, LIR_Opr index)
-  : _index(index), _array(NULL), _throw_index_out_of_bounds_exception(true) {
-  assert(info != NULL, "must have info");
-  _info = new CodeEmitInfo(info);
-}
-
-void RangeCheckStub::emit_code(LIR_Assembler* ce) {
-  __ bind(_entry);
-  if (_info->deoptimize_on_exception()) {
-    address a = Runtime1::entry_for(Runtime1::predicate_failed_trap_id);
-    __ far_call(RuntimeAddress(a));
-    ce->add_call_info_here(_info);
-    ce->verify_oop_map(_info);
-    debug_only(__ should_not_reach_here());
-    return;
-  }
-
-  if (_index->is_cpu_register()) {
-    __ mv(t0, _index->as_register());
-  } else {
-    __ mv(t0, _index->as_jint());
-  }
-  Runtime1::StubID stub_id;
-  if (_throw_index_out_of_bounds_exception) {
-    stub_id = Runtime1::throw_index_exception_id;
-  } else {
-    assert(_array != NULL, "sanity");
-    __ mv(t1, _array->as_pointer_register());
-    stub_id = Runtime1::throw_range_check_failed_id;
-  }
-  RuntimeAddress target(Runtime1::entry_for(stub_id));
-  __ relocate(target.rspec(), [&] {
-    int32_t offset;
-    __ la_patchable(ra, target, offset);
-    __ jalr(ra, ra, offset);
-  });
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-  debug_only(__ should_not_reach_here());
-}
-
-PredicateFailedStub::PredicateFailedStub(CodeEmitInfo* info) {
-  _info = new CodeEmitInfo(info);
-}
-
-void PredicateFailedStub::emit_code(LIR_Assembler* ce) {
-  __ bind(_entry);
-  address a = Runtime1::entry_for(Runtime1::predicate_failed_trap_id);
-  __ far_call(RuntimeAddress(a));
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-  debug_only(__ should_not_reach_here());
-}
-
-void DivByZeroStub::emit_code(LIR_Assembler* ce) {
-  if (_offset != -1) {
-    ce->compilation()->implicit_exception_table()->append(_offset, __ offset());
-  }
-  __ bind(_entry);
-  __ far_call(Address(Runtime1::entry_for(Runtime1::throw_div0_exception_id), relocInfo::runtime_call_type));
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-#ifdef ASSERT
-  __ should_not_reach_here();
-#endif
-}
-
-// Implementation of NewInstanceStub
-NewInstanceStub::NewInstanceStub(LIR_Opr klass_reg, LIR_Opr result, ciInstanceKlass* klass, CodeEmitInfo* info, Runtime1::StubID stub_id) {
-  _result = result;
-  _klass = klass;
-  _klass_reg = klass_reg;
-  _info = new CodeEmitInfo(info);
-  assert(stub_id == Runtime1::new_instance_id                 ||
-         stub_id == Runtime1::fast_new_instance_id            ||
-         stub_id == Runtime1::fast_new_instance_init_check_id,
-         "need new_instance id");
-  _stub_id = stub_id;
-}
-
-void NewInstanceStub::emit_code(LIR_Assembler* ce) {
-  assert(__ rsp_offset() == 0, "frame size should be fixed");
-  __ bind(_entry);
-  __ mv(x13, _klass_reg->as_register());
-  __ far_call(RuntimeAddress(Runtime1::entry_for(_stub_id)));
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-  assert(_result->as_register() == x10, "result must in x10");
-  __ j(_continuation);
-}
-
-// Implementation of NewTypeArrayStub
-NewTypeArrayStub::NewTypeArrayStub(LIR_Opr klass_reg, LIR_Opr length, LIR_Opr result, CodeEmitInfo* info) {
-  _klass_reg = klass_reg;
-  _length = length;
-  _result = result;
-  _info = new CodeEmitInfo(info);
-}
-
-void NewTypeArrayStub::emit_code(LIR_Assembler* ce) {
-  assert(__ rsp_offset() == 0, "frame size should be fixed");
-  __ bind(_entry);
-  assert(_length->as_register() == x9, "length must in x9");
-  assert(_klass_reg->as_register() == x13, "klass_reg must in x13");
-  __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::new_type_array_id)));
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-  assert(_result->as_register() == x10, "result must in x10");
-  __ j(_continuation);
-}
-
-// Implementation of NewObjectArrayStub
-NewObjectArrayStub::NewObjectArrayStub(LIR_Opr klass_reg, LIR_Opr length, LIR_Opr result, CodeEmitInfo* info) {
-  _klass_reg = klass_reg;
-  _result = result;
-  _length = length;
-  _info = new CodeEmitInfo(info);
-}
-
-void NewObjectArrayStub::emit_code(LIR_Assembler* ce) {
-  assert(__ rsp_offset() == 0, "frame size should be fixed");
-  __ bind(_entry);
-  assert(_length->as_register() == x9, "length must in x9");
-  assert(_klass_reg->as_register() == x13, "klass_reg must in x13");
-  __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::new_object_array_id)));
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-  assert(_result->as_register() == x10, "result must in x10");
-  __ j(_continuation);
-}
-
-// Implementation of MonitorAccessStubs
-MonitorEnterStub::MonitorEnterStub(LIR_Opr obj_reg, LIR_Opr lock_reg, CodeEmitInfo* info)
-: MonitorAccessStub(obj_reg, lock_reg) {
-  _info = new CodeEmitInfo(info);
-}
-
-void MonitorEnterStub::emit_code(LIR_Assembler* ce) {
-  assert(__ rsp_offset() == 0, "frame size should be fixed");
-  __ bind(_entry);
-  ce->store_parameter(_obj_reg->as_register(),  1);
-  ce->store_parameter(_lock_reg->as_register(), 0);
-  Runtime1::StubID enter_id;
-  if (ce->compilation()->has_fpu_code()) {
-    enter_id = Runtime1::monitorenter_id;
-  } else {
-    enter_id = Runtime1::monitorenter_nofpu_id;
-  }
-  __ far_call(RuntimeAddress(Runtime1::entry_for(enter_id)));
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-  __ j(_continuation);
-}
-
-void MonitorExitStub::emit_code(LIR_Assembler* ce) {
-  __ bind(_entry);
-  if (_compute_lock) {
-    // lock_reg was destroyed by fast unlocking attempt => recompute it
-    ce->monitor_address(_monitor_ix, _lock_reg);
-  }
-  ce->store_parameter(_lock_reg->as_register(), 0);
-  // note: non-blocking leaf routine => no call info needed
-  Runtime1::StubID exit_id;
-  if (ce->compilation()->has_fpu_code()) {
-    exit_id = Runtime1::monitorexit_id;
-  } else {
-    exit_id = Runtime1::monitorexit_nofpu_id;
-  }
-  __ la(ra, _continuation);
-  __ far_jump(RuntimeAddress(Runtime1::entry_for(exit_id)));
-}
-
-// Implementation of patching:
-// - Copy the code at given offset to an inlined buffer (first the bytes, then the number of bytes)
-// - Replace original code with a call to the stub
-// At Runtime:
-// - call to stub, jump to runtime
-// - in runtime: preserve all registers (rspecially objects, i.e., source and destination object)
-// - in runtime: after initializing class, restore original code, reexecute instruction
-
-int PatchingStub::_patch_info_offset = -NativeGeneralJump::instruction_size;
-
-void PatchingStub::align_patch_site(MacroAssembler* masm) {}
-
-void PatchingStub::emit_code(LIR_Assembler* ce) {
-  assert(false, "RISCV should not use C1 runtime patching");
-}
-
-void DeoptimizeStub::emit_code(LIR_Assembler* ce) {
-  __ bind(_entry);
-  ce->store_parameter(_trap_request, 0);
-  __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::deoptimize_id)));
-  ce->add_call_info_here(_info);
-  DEBUG_ONLY(__ should_not_reach_here());
-}
-
-void ImplicitNullCheckStub::emit_code(LIR_Assembler* ce) {
-  address a = NULL;
-  if (_info->deoptimize_on_exception()) {
-    // Deoptimize, do not throw the exception, because it is probably wrong to do it here.
-    a = Runtime1::entry_for(Runtime1::predicate_failed_trap_id);
-  } else {
-    a = Runtime1::entry_for(Runtime1::throw_null_pointer_exception_id);
-  }
-
-  ce->compilation()->implicit_exception_table()->append(_offset, __ offset());
-  __ bind(_entry);
-  __ far_call(RuntimeAddress(a));
-  ce->add_call_info_here(_info);
-  ce->verify_oop_map(_info);
-  debug_only(__ should_not_reach_here());
-}
-
-void SimpleExceptionStub::emit_code(LIR_Assembler* ce) {
-  assert(__ rsp_offset() == 0, "frame size should be fixed");
-
-  __ bind(_entry);
-  // pass the object in a tmp register because all other registers
-  // must be preserved
-  if (_obj->is_cpu_register()) {
-    __ mv(t0, _obj->as_register());
-  }
-  __ far_call(RuntimeAddress(Runtime1::entry_for(_stub)), NULL, t1);
-  ce->add_call_info_here(_info);
-  debug_only(__ should_not_reach_here());
-}
-
-void ArrayCopyStub::emit_code(LIR_Assembler* ce) {
-  // ---------------slow case: call to native-----------------
-  __ bind(_entry);
-  // Figure out where the args should go
-  // This should really convert the IntrinsicID to the Method* and signature
-  // but I don't know how to do that.
-  const int args_num = 5;
-  VMRegPair args[args_num];
-  BasicType signature[args_num] = { T_OBJECT, T_INT, T_OBJECT, T_INT, T_INT };
-  SharedRuntime::java_calling_convention(signature, args, args_num);
-
-  // push parameters
-  Register r[args_num];
-  r[0] = src()->as_register();
-  r[1] = src_pos()->as_register();
-  r[2] = dst()->as_register();
-  r[3] = dst_pos()->as_register();
-  r[4] = length()->as_register();
-
-  // next registers will get stored on the stack
-  for (int j = 0; j < args_num; j++) {
-    VMReg r_1 = args[j].first();
-    if (r_1->is_stack()) {
-      int st_off = r_1->reg2stack() * wordSize;
-      __ sd(r[j], Address(sp, st_off));
-    } else {
-      assert(r[j] == args[j].first()->as_Register(), "Wrong register for arg");
-    }
-  }
-
-  ce->align_call(lir_static_call);
-
-  ce->emit_static_call_stub();
-  if (ce->compilation()->bailed_out()) {
-    return; // CodeCache is full
-  }
-  Address resolve(SharedRuntime::get_resolve_static_call_stub(),
-                  relocInfo::static_call_type);
-  address call = __ trampoline_call(resolve);
-  if (call == NULL) {
-    ce->bailout("trampoline stub overflow");
-    return;
-  }
-  ce->add_call_info_here(info());
-
-#ifndef PRODUCT
-  if (PrintC1Statistics) {
-    __ la(t1, ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt));
-    __ incrementw(Address(t1));
-  }
-#endif
-
-  __ j(_continuation);
-}
-
-#undef __

src/hotspot/cpu/riscv/c1_Defs_riscv.hpp

@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_DEFS_RISCV_HPP
-#define CPU_RISCV_C1_DEFS_RISCV_HPP
-
-// native word offsets from memory address (little endian)
-enum {
-  pd_lo_word_offset_in_bytes = 0,
-  pd_hi_word_offset_in_bytes = BytesPerWord
-};
-
-// explicit rounding operations are required to implement the strictFP mode
-enum {
-  pd_strict_fp_requires_explicit_rounding = false
-};
-
-// registers
-enum {
-  pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers,       // number of registers used during code emission
-  pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers,  // number of float registers used during code emission
-
-  // caller saved
-  pd_nof_caller_save_cpu_regs_frame_map = 13, // number of registers killed by calls
-  pd_nof_caller_save_fpu_regs_frame_map = 32, // number of float registers killed by calls
-
-  pd_first_callee_saved_reg = pd_nof_caller_save_cpu_regs_frame_map,
-  pd_last_callee_saved_reg = 21,
-
-  pd_last_allocatable_cpu_reg = pd_nof_caller_save_cpu_regs_frame_map - 1,
-
-  pd_nof_cpu_regs_reg_alloc
-    = pd_nof_caller_save_cpu_regs_frame_map,  // number of registers that are visible to register allocator
-  pd_nof_fpu_regs_reg_alloc = 32,  // number of float registers that are visible to register allocator
-
-  pd_nof_cpu_regs_linearscan = 32, // number of registers visible to linear scan
-  pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of float registers visible to linear scan
-  pd_nof_xmm_regs_linearscan = 0, // don't have vector registers
-
-  pd_first_cpu_reg  = 0,
-  pd_last_cpu_reg   = pd_nof_cpu_regs_reg_alloc - 1,
-  pd_first_byte_reg = 0,
-  pd_last_byte_reg  = pd_nof_cpu_regs_reg_alloc - 1,
-
-  pd_first_fpu_reg  = pd_nof_cpu_regs_frame_map,
-  pd_last_fpu_reg   = pd_first_fpu_reg + 31,
-
-  pd_first_callee_saved_fpu_reg_1 = 8 + pd_first_fpu_reg,
-  pd_last_callee_saved_fpu_reg_1  = 9 + pd_first_fpu_reg,
-  pd_first_callee_saved_fpu_reg_2 = 18 + pd_first_fpu_reg,
-  pd_last_callee_saved_fpu_reg_2  = 27 + pd_first_fpu_reg
-};
-
-
-// Encoding of float value in debug info.  This is true on x86 where
-// floats are extended to doubles when stored in the stack, false for
-// RISCV where floats and doubles are stored in their native form.
-enum {
-  pd_float_saved_as_double = false
-};
-
-#endif // CPU_RISCV_C1_DEFS_RISCV_HPP

src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.cpp

@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-//--------------------------------------------------------
-//               FpuStackSim
-//--------------------------------------------------------
-
-// No FPU stack on RISCV

src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.hpp

@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP
-#define CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP
-
-// No FPU stack on RISCV
-class FpuStackSim;
-
-#endif // CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP

src/hotspot/cpu/riscv/c1_FrameMap_riscv.cpp

@@ -1,388 +0,0 @@
-/*
- * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "c1/c1_FrameMap.hpp"
-#include "c1/c1_LIR.hpp"
-#include "runtime/sharedRuntime.hpp"
-#include "vmreg_riscv.inline.hpp"
-
-LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
-  LIR_Opr opr = LIR_OprFact::illegalOpr;
-  VMReg r_1 = reg->first();
-  VMReg r_2 = reg->second();
-  if (r_1->is_stack()) {
-    // Convert stack slot to an SP offset
-    // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
-    // so we must add it in here.
-    int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
-    opr = LIR_OprFact::address(new LIR_Address(sp_opr, st_off, type));
-  } else if (r_1->is_Register()) {
-    Register reg1 = r_1->as_Register();
-    if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
-      Register reg2 = r_2->as_Register();
-      assert(reg2 == reg1, "must be same register");
-      opr = as_long_opr(reg1);
-    } else if (is_reference_type(type)) {
-      opr = as_oop_opr(reg1);
-    } else if (type == T_METADATA) {
-      opr = as_metadata_opr(reg1);
-    } else if (type == T_ADDRESS) {
-      opr = as_address_opr(reg1);
-    } else {
-      opr = as_opr(reg1);
-    }
-  } else if (r_1->is_FloatRegister()) {
-    assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
-    int num = r_1->as_FloatRegister()->encoding();
-    if (type == T_FLOAT) {
-      opr = LIR_OprFact::single_fpu(num);
-    } else {
-      opr = LIR_OprFact::double_fpu(num);
-    }
-  } else {
-    ShouldNotReachHere();
-  }
-  return opr;
-}
-
-LIR_Opr FrameMap::zr_opr;
-LIR_Opr FrameMap::r1_opr;
-LIR_Opr FrameMap::r2_opr;
-LIR_Opr FrameMap::r3_opr;
-LIR_Opr FrameMap::r4_opr;
-LIR_Opr FrameMap::r5_opr;
-LIR_Opr FrameMap::r6_opr;
-LIR_Opr FrameMap::r7_opr;
-LIR_Opr FrameMap::r8_opr;
-LIR_Opr FrameMap::r9_opr;
-LIR_Opr FrameMap::r10_opr;
-LIR_Opr FrameMap::r11_opr;
-LIR_Opr FrameMap::r12_opr;
-LIR_Opr FrameMap::r13_opr;
-LIR_Opr FrameMap::r14_opr;
-LIR_Opr FrameMap::r15_opr;
-LIR_Opr FrameMap::r16_opr;
-LIR_Opr FrameMap::r17_opr;
-LIR_Opr FrameMap::r18_opr;
-LIR_Opr FrameMap::r19_opr;
-LIR_Opr FrameMap::r20_opr;
-LIR_Opr FrameMap::r21_opr;
-LIR_Opr FrameMap::r22_opr;
-LIR_Opr FrameMap::r23_opr;
-LIR_Opr FrameMap::r24_opr;
-LIR_Opr FrameMap::r25_opr;
-LIR_Opr FrameMap::r26_opr;
-LIR_Opr FrameMap::r27_opr;
-LIR_Opr FrameMap::r28_opr;
-LIR_Opr FrameMap::r29_opr;
-LIR_Opr FrameMap::r30_opr;
-LIR_Opr FrameMap::r31_opr;
-
-LIR_Opr FrameMap::fp_opr;
-LIR_Opr FrameMap::sp_opr;
-
-LIR_Opr FrameMap::receiver_opr;
-
-LIR_Opr FrameMap::zr_oop_opr;
-LIR_Opr FrameMap::r1_oop_opr;
-LIR_Opr FrameMap::r2_oop_opr;
-LIR_Opr FrameMap::r3_oop_opr;
-LIR_Opr FrameMap::r4_oop_opr;
-LIR_Opr FrameMap::r5_oop_opr;
-LIR_Opr FrameMap::r6_oop_opr;
-LIR_Opr FrameMap::r7_oop_opr;
-LIR_Opr FrameMap::r8_oop_opr;
-LIR_Opr FrameMap::r9_oop_opr;
-LIR_Opr FrameMap::r10_oop_opr;
-LIR_Opr FrameMap::r11_oop_opr;
-LIR_Opr FrameMap::r12_oop_opr;
-LIR_Opr FrameMap::r13_oop_opr;
-LIR_Opr FrameMap::r14_oop_opr;
-LIR_Opr FrameMap::r15_oop_opr;
-LIR_Opr FrameMap::r16_oop_opr;
-LIR_Opr FrameMap::r17_oop_opr;
-LIR_Opr FrameMap::r18_oop_opr;
-LIR_Opr FrameMap::r19_oop_opr;
-LIR_Opr FrameMap::r20_oop_opr;
-LIR_Opr FrameMap::r21_oop_opr;
-LIR_Opr FrameMap::r22_oop_opr;
-LIR_Opr FrameMap::r23_oop_opr;
-LIR_Opr FrameMap::r24_oop_opr;
-LIR_Opr FrameMap::r25_oop_opr;
-LIR_Opr FrameMap::r26_oop_opr;
-LIR_Opr FrameMap::r27_oop_opr;
-LIR_Opr FrameMap::r28_oop_opr;
-LIR_Opr FrameMap::r29_oop_opr;
-LIR_Opr FrameMap::r30_oop_opr;
-LIR_Opr FrameMap::r31_oop_opr;
-
-LIR_Opr FrameMap::t0_opr;
-LIR_Opr FrameMap::t1_opr;
-LIR_Opr FrameMap::t0_long_opr;
-LIR_Opr FrameMap::t1_long_opr;
-
-LIR_Opr FrameMap::r10_metadata_opr;
-LIR_Opr FrameMap::r11_metadata_opr;
-LIR_Opr FrameMap::r12_metadata_opr;
-LIR_Opr FrameMap::r13_metadata_opr;
-LIR_Opr FrameMap::r14_metadata_opr;
-LIR_Opr FrameMap::r15_metadata_opr;
-
-LIR_Opr FrameMap::long10_opr;
-LIR_Opr FrameMap::long11_opr;
-LIR_Opr FrameMap::fpu10_float_opr;
-LIR_Opr FrameMap::fpu10_double_opr;
-
-LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
-LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
-
-//--------------------------------------------------------
-//               FrameMap
-//--------------------------------------------------------
-// |---f31--|
-// |---..---|
-// |---f28--|
-// |---f27--|<---pd_last_callee_saved_fpu_reg_2
-// |---..---|
-// |---f18--|<---pd_first_callee_saved_fpu_reg_2
-// |---f17--|
-// |---..---|
-// |---f10--|
-// |---f9---|<---pd_last_callee_saved_fpu_reg_1
-// |---f8---|<---pd_first_callee_saved_fpu_reg_1
-// |---f7---|
-// |---..---|
-// |---f0---|
-// |---x27--|
-// |---x23--|
-// |---x8---|
-// |---x4---|
-// |---x3---|
-// |---x2---|
-// |---x1---|
-// |---x0---|
-// |---x26--|<---pd_last_callee_saved_reg
-// |---..---|
-// |---x18--|
-// |---x9---|<---pd_first_callee_saved_reg
-// |---x31--|
-// |---..---|
-// |---x28--|
-// |---x17--|
-// |---..---|
-// |---x10--|
-// |---x7---|
-
-void FrameMap::initialize() {
-  assert(!_init_done, "once");
-
-  int i = 0;
-
-  // caller save register
-  map_register(i, x7);  r7_opr  = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x10); r10_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x11); r11_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x12); r12_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x13); r13_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x14); r14_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x15); r15_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x16); r16_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x17); r17_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x28); r28_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x29); r29_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x30); r30_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x31); r31_opr = LIR_OprFact::single_cpu(i); i++;
-
-  // callee save register
-  map_register(i, x9);  r9_opr  = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x18); r18_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x19); r19_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x20); r20_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x21); r21_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x22); r22_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x24); r24_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x25); r25_opr = LIR_OprFact::single_cpu(i); i++;
-  map_register(i, x26); r26_opr = LIR_OprFact::single_cpu(i); i++;
-
-  // special register
-  map_register(i, x0);  zr_opr  = LIR_OprFact::single_cpu(i); i++;  // zr
-  map_register(i, x1);  r1_opr  = LIR_OprFact::single_cpu(i); i++;  // ra
-  map_register(i, x2);  r2_opr  = LIR_OprFact::single_cpu(i); i++;  // sp
-  map_register(i, x3);  r3_opr  = LIR_OprFact::single_cpu(i); i++;  // gp
-  map_register(i, x4);  r4_opr  = LIR_OprFact::single_cpu(i); i++;  // thread
-  map_register(i, x8);  r8_opr  = LIR_OprFact::single_cpu(i); i++;  // fp
-  map_register(i, x23); r23_opr = LIR_OprFact::single_cpu(i); i++;  // java thread
-  map_register(i, x27); r27_opr = LIR_OprFact::single_cpu(i); i++;  // heapbase
-
-  // tmp register
-  map_register(i, x5);  r5_opr  = LIR_OprFact::single_cpu(i); i++;  // t0
-  map_register(i, x6);  r6_opr  = LIR_OprFact::single_cpu(i); i++;  // t1
-
-  t0_opr = r5_opr;
-  t1_opr = r6_opr;
-  t0_long_opr = LIR_OprFact::double_cpu(r5_opr->cpu_regnr(), r5_opr->cpu_regnr());
-  t1_long_opr = LIR_OprFact::double_cpu(r6_opr->cpu_regnr(), r6_opr->cpu_regnr());
-
-  long10_opr  = LIR_OprFact::double_cpu(r10_opr->cpu_regnr(), r10_opr->cpu_regnr());
-  long11_opr  = LIR_OprFact::double_cpu(r11_opr->cpu_regnr(), r11_opr->cpu_regnr());
-
-  fpu10_float_opr   = LIR_OprFact::single_fpu(10);
-  fpu10_double_opr  = LIR_OprFact::double_fpu(10);
-
-  i = 0;
-  _caller_save_cpu_regs[i++]  = r7_opr;
-  _caller_save_cpu_regs[i++]  = r10_opr;
-  _caller_save_cpu_regs[i++]  = r11_opr;
-  _caller_save_cpu_regs[i++]  = r12_opr;
-  _caller_save_cpu_regs[i++]  = r13_opr;
-  _caller_save_cpu_regs[i++]  = r14_opr;
-  _caller_save_cpu_regs[i++]  = r15_opr;
-  _caller_save_cpu_regs[i++]  = r16_opr;
-  _caller_save_cpu_regs[i++]  = r17_opr;
-  _caller_save_cpu_regs[i++]  = r28_opr;
-  _caller_save_cpu_regs[i++]  = r29_opr;
-  _caller_save_cpu_regs[i++]  = r30_opr;
-  _caller_save_cpu_regs[i++]  = r31_opr;
-
-  _init_done = true;
-
-  zr_oop_opr  = as_oop_opr(x0);
-  r1_oop_opr  = as_oop_opr(x1);
-  r2_oop_opr  = as_oop_opr(x2);
-  r3_oop_opr  = as_oop_opr(x3);
-  r4_oop_opr  = as_oop_opr(x4);
-  r5_oop_opr  = as_oop_opr(x5);
-  r6_oop_opr  = as_oop_opr(x6);
-  r7_oop_opr  = as_oop_opr(x7);
-  r8_oop_opr  = as_oop_opr(x8);
-  r9_oop_opr  = as_oop_opr(x9);
-  r10_oop_opr = as_oop_opr(x10);
-  r11_oop_opr = as_oop_opr(x11);
-  r12_oop_opr = as_oop_opr(x12);
-  r13_oop_opr = as_oop_opr(x13);
-  r14_oop_opr = as_oop_opr(x14);
-  r15_oop_opr = as_oop_opr(x15);
-  r16_oop_opr = as_oop_opr(x16);
-  r17_oop_opr = as_oop_opr(x17);
-  r18_oop_opr = as_oop_opr(x18);
-  r19_oop_opr = as_oop_opr(x19);
-  r20_oop_opr = as_oop_opr(x20);
-  r21_oop_opr = as_oop_opr(x21);
-  r22_oop_opr = as_oop_opr(x22);
-  r23_oop_opr = as_oop_opr(x23);
-  r24_oop_opr = as_oop_opr(x24);
-  r25_oop_opr = as_oop_opr(x25);
-  r26_oop_opr = as_oop_opr(x26);
-  r27_oop_opr = as_oop_opr(x27);
-  r28_oop_opr = as_oop_opr(x28);
-  r29_oop_opr = as_oop_opr(x29);
-  r30_oop_opr = as_oop_opr(x30);
-  r31_oop_opr = as_oop_opr(x31);
-
-  r10_metadata_opr = as_metadata_opr(x10);
-  r11_metadata_opr = as_metadata_opr(x11);
-  r12_metadata_opr = as_metadata_opr(x12);
-  r13_metadata_opr = as_metadata_opr(x13);
-  r14_metadata_opr = as_metadata_opr(x14);
-  r15_metadata_opr = as_metadata_opr(x15);
-
-  sp_opr = as_pointer_opr(sp);
-  fp_opr = as_pointer_opr(fp);
-
-  VMRegPair regs;
-  BasicType sig_bt = T_OBJECT;
-  SharedRuntime::java_calling_convention(&sig_bt, &regs, 1);
-  receiver_opr = as_oop_opr(regs.first()->as_Register());
-
-  for (i = 0; i < nof_caller_save_fpu_regs; i++) {
-    _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
-  }
-}
-
-
-Address FrameMap::make_new_address(ByteSize sp_offset) const {
-  return Address(sp, in_bytes(sp_offset));
-}
-
-
-// ----------------mapping-----------------------
-// all mapping is based on fp addressing, except for simple leaf methods where we access
-// the locals sp based (and no frame is built)
-
-
-// Frame for simple leaf methods (quick entries)
-//
-//   +----------+
-//   | ret addr |   <- TOS
-//   +----------+
-//   | args     |
-//   | ......   |
-
-// Frame for standard methods
-//
-//   | .........|  <- TOS
-//   | locals   |
-//   +----------+
-//   |  old fp, |
-//   +----------+
-//   | ret addr |
-//   +----------+
-//   |  args    |  <- FP
-//   | .........|
-
-
-// For OopMaps, map a local variable or spill index to an VMRegImpl name.
-// This is the offset from sp() in the frame of the slot for the index,
-// skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
-//
-//           framesize +
-//           stack0         stack0          0  <- VMReg
-//             |              | <registers> |
-//  ...........|..............|.............|
-//      0 1 2 3 x x 4 5 6 ... |                <- local indices
-//      ^           ^        sp()                 ( x x indicate link
-//      |           |                               and return addr)
-//  arguments   non-argument locals
-
-
-VMReg FrameMap::fpu_regname (int n) {
-  // Return the OptoReg name for the fpu stack slot "n"
-  // A spilled fpu stack slot comprises to two single-word OptoReg's.
-  return as_FloatRegister(n)->as_VMReg();
-}
-
-LIR_Opr FrameMap::stack_pointer() {
-  return FrameMap::sp_opr;
-}
-
-// JSR 292
-LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
-  return LIR_OprFact::illegalOpr;  // Not needed on riscv
-}
-
-bool FrameMap::validate_frame() {
-  return true;
-}

src/hotspot/cpu/riscv/c1_FrameMap_riscv.hpp

@@ -1,148 +0,0 @@
-/*
- * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_FRAMEMAP_RISCV_HPP
-#define CPU_RISCV_C1_FRAMEMAP_RISCV_HPP
-
-//  On RISCV the frame looks as follows:
-//
-//  +-----------------------------+---------+----------------------------------------+----------------+-----------
-//  | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
-//  +-----------------------------+---------+----------------------------------------+----------------+-----------
-
- public:
-  static const int pd_c_runtime_reserved_arg_size;
-
-  enum {
-    first_available_sp_in_frame = 0,
-    frame_pad_in_bytes = 16,
-    nof_reg_args = 8
-  };
-
- public:
-  static LIR_Opr receiver_opr;
-
-  static LIR_Opr zr_opr;
-  static LIR_Opr r1_opr;
-  static LIR_Opr r2_opr;
-  static LIR_Opr r3_opr;
-  static LIR_Opr r4_opr;
-  static LIR_Opr r5_opr;
-  static LIR_Opr r6_opr;
-  static LIR_Opr r7_opr;
-  static LIR_Opr r8_opr;
-  static LIR_Opr r9_opr;
-  static LIR_Opr r10_opr;
-  static LIR_Opr r11_opr;
-  static LIR_Opr r12_opr;
-  static LIR_Opr r13_opr;
-  static LIR_Opr r14_opr;
-  static LIR_Opr r15_opr;
-  static LIR_Opr r16_opr;
-  static LIR_Opr r17_opr;
-  static LIR_Opr r18_opr;
-  static LIR_Opr r19_opr;
-  static LIR_Opr r20_opr;
-  static LIR_Opr r21_opr;
-  static LIR_Opr r22_opr;
-  static LIR_Opr r23_opr;
-  static LIR_Opr r24_opr;
-  static LIR_Opr r25_opr;
-  static LIR_Opr r26_opr;
-  static LIR_Opr r27_opr;
-  static LIR_Opr r28_opr;
-  static LIR_Opr r29_opr;
-  static LIR_Opr r30_opr;
-  static LIR_Opr r31_opr;
-  static LIR_Opr fp_opr;
-  static LIR_Opr sp_opr;
-
-  static LIR_Opr zr_oop_opr;
-  static LIR_Opr r1_oop_opr;
-  static LIR_Opr r2_oop_opr;
-  static LIR_Opr r3_oop_opr;
-  static LIR_Opr r4_oop_opr;
-  static LIR_Opr r5_oop_opr;
-  static LIR_Opr r6_oop_opr;
-  static LIR_Opr r7_oop_opr;
-  static LIR_Opr r8_oop_opr;
-  static LIR_Opr r9_oop_opr;
-  static LIR_Opr r10_oop_opr;
-  static LIR_Opr r11_oop_opr;
-  static LIR_Opr r12_oop_opr;
-  static LIR_Opr r13_oop_opr;
-  static LIR_Opr r14_oop_opr;
-  static LIR_Opr r15_oop_opr;
-  static LIR_Opr r16_oop_opr;
-  static LIR_Opr r17_oop_opr;
-  static LIR_Opr r18_oop_opr;
-  static LIR_Opr r19_oop_opr;
-  static LIR_Opr r20_oop_opr;
-  static LIR_Opr r21_oop_opr;
-  static LIR_Opr r22_oop_opr;
-  static LIR_Opr r23_oop_opr;
-  static LIR_Opr r24_oop_opr;
-  static LIR_Opr r25_oop_opr;
-  static LIR_Opr r26_oop_opr;
-  static LIR_Opr r27_oop_opr;
-  static LIR_Opr r28_oop_opr;
-  static LIR_Opr r29_oop_opr;
-  static LIR_Opr r30_oop_opr;
-  static LIR_Opr r31_oop_opr;
-
-  static LIR_Opr t0_opr;
-  static LIR_Opr t1_opr;
-  static LIR_Opr t0_long_opr;
-  static LIR_Opr t1_long_opr;
-
-  static LIR_Opr r10_metadata_opr;
-  static LIR_Opr r11_metadata_opr;
-  static LIR_Opr r12_metadata_opr;
-  static LIR_Opr r13_metadata_opr;
-  static LIR_Opr r14_metadata_opr;
-  static LIR_Opr r15_metadata_opr;
-
-  static LIR_Opr long10_opr;
-  static LIR_Opr long11_opr;
-  static LIR_Opr fpu10_float_opr;
-  static LIR_Opr fpu10_double_opr;
-
-  static LIR_Opr as_long_opr(Register r) {
-    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
-  }
-  static LIR_Opr as_pointer_opr(Register r) {
-    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
-  }
-
-  // VMReg name for spilled physical FPU stack slot n
-  static VMReg fpu_regname(int n);
-
-  static bool is_caller_save_register(LIR_Opr opr) { return true; }
-  static bool is_caller_save_register(Register r)  { return true; }
-
-  static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; }
-  static int last_cpu_reg()             { return pd_last_cpu_reg; }
-
-#endif // CPU_RISCV_C1_FRAMEMAP_RISCV_HPP

src/hotspot/cpu/riscv/c1_LIRAssembler_arith_riscv.cpp

@@ -1,281 +0,0 @@
-/*
- * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "asm/assembler.hpp"
-#include "c1/c1_LIRAssembler.hpp"
-#include "c1/c1_MacroAssembler.hpp"
-
-#ifndef PRODUCT
-#define COMMENT(x)   do { __ block_comment(x); } while (0)
-#else
-#define COMMENT(x)
-#endif
-
-#define __ _masm->
-
-void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal,
-                                    LIR_Opr result, CodeEmitInfo* info) {
-  // opcode check
-  assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
-  bool is_irem = (code == lir_irem);
-  // opreand check
-  assert(left->is_single_cpu(), "left must be a register");
-  assert(right->is_single_cpu() || right->is_constant(), "right must be a register or constant");
-  assert(result->is_single_cpu(), "result must be a register");
-  Register lreg = left->as_register();
-  Register dreg = result->as_register();
-
-  // power-of-2 constant check and codegen
-  if (right->is_constant()) {
-    int c = right->as_constant_ptr()->as_jint();
-    assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
-    if (is_irem) {
-      if (c == 1) {
-        // move 0 to dreg if divisor is 1
-        __ mv(dreg, zr);
-      } else {
-        unsigned int shift = exact_log2(c);
-        __ sraiw(t0, lreg, 0x1f);
-        __ srliw(t0, t0, BitsPerInt - shift);
-        __ addw(t1, lreg, t0);
-        if (Assembler::is_simm12(c - 1)) {
-          __ andi(t1, t1, c - 1);
-        } else {
-          __ zero_extend(t1, t1, shift);
-        }
-        __ subw(dreg, t1, t0);
-      }
-    } else {
-      if (c == 1) {
-        // move lreg to dreg if divisor is 1
-        __ mv(dreg, lreg);
-      } else {
-        unsigned int shift = exact_log2(c);
-        __ sraiw(t0, lreg, 0x1f);
-        if (Assembler::is_simm12(c - 1)) {
-          __ andi(t0, t0, c - 1);
-        } else {
-          __ zero_extend(t0, t0, shift);
-        }
-        __ addw(dreg, t0, lreg);
-        __ sraiw(dreg, dreg, shift);
-      }
-    }
-  } else {
-    Register rreg = right->as_register();
-    __ corrected_idivl(dreg, lreg, rreg, is_irem);
-  }
-}
-
-void LIR_Assembler::arith_op_single_cpu_right_constant(LIR_Code code, LIR_Opr left, LIR_Opr right,
-                                                       Register lreg, Register dreg) {
-  // cpu register - constant
-  jlong c;
-
-  switch (right->type()) {
-    case T_LONG:
-      c = right->as_constant_ptr()->as_jlong(); break;
-    case T_INT:     // fall through
-    case T_ADDRESS:
-      c = right->as_constant_ptr()->as_jint(); break;
-    default:
-      ShouldNotReachHere();
-      c = 0;   // unreachable
-  }
-
-  assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
-  if (c == 0 && dreg == lreg) {
-    COMMENT("effective nop elided");
-    return;
-  }
-  switch (left->type()) {
-    case T_INT:
-      switch (code) {
-        case lir_add: __ addw(dreg, lreg, c); break;
-        case lir_sub: __ subw(dreg, lreg, c); break;
-        default:      ShouldNotReachHere();
-      }
-    break;
-    case T_OBJECT:  // fall through
-    case T_ADDRESS:
-      switch (code) {
-        case lir_add: __ add(dreg, lreg, c); break;
-        case lir_sub: __ sub(dreg, lreg, c); break;
-        default:      ShouldNotReachHere();
-      }
-    break;
-    default:
-      ShouldNotReachHere();
-  }
-}
-
-void LIR_Assembler::arith_op_single_cpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
-  Register lreg = left->as_register();
-  Register dreg = as_reg(dest);
-
-  if (right->is_single_cpu()) {
-    // cpu register - cpu register
-    assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT, "should be");
-    Register rreg = right->as_register();
-    switch (code) {
-      case lir_add: __ addw(dest->as_register(), lreg, rreg); break;
-      case lir_sub: __ subw(dest->as_register(), lreg, rreg); break;
-      case lir_mul: __ mulw(dest->as_register(), lreg, rreg); break;
-      default:      ShouldNotReachHere();
-    }
-  } else if (right->is_double_cpu()) {
-    Register rreg = right->as_register_lo();
-    // sigle_cpu + double_cpu; can happen with obj_long
-    assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
-    switch (code) {
-      case lir_add: __ add(dreg, lreg, rreg); break;
-      case lir_sub: __ sub(dreg, lreg, rreg); break;
-      default:      ShouldNotReachHere();
-    }
-  } else if (right->is_constant()) {
-    arith_op_single_cpu_right_constant(code, left, right, lreg, dreg);
-  } else {
-    ShouldNotReachHere();
-  }
-}
-
-void LIR_Assembler::arith_op_double_cpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
-  Register lreg_lo = left->as_register_lo();
-
-  if (right->is_double_cpu()) {
-    // cpu register - cpu register
-    Register rreg_lo = right->as_register_lo();
-    switch (code) {
-      case lir_add: __ add(dest->as_register_lo(), lreg_lo, rreg_lo); break;
-      case lir_sub: __ sub(dest->as_register_lo(), lreg_lo, rreg_lo); break;
-      case lir_mul: __ mul(dest->as_register_lo(), lreg_lo, rreg_lo); break;
-      case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false); break;
-      case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true); break;
-      default:
-        ShouldNotReachHere();
-    }
-  } else if (right->is_constant()) {
-    jlong c = right->as_constant_ptr()->as_jlong();
-    Register dreg = as_reg(dest);
-    switch (code) {
-      case lir_add: // fall through
-      case lir_sub:
-        if (c == 0 && dreg == lreg_lo) {
-          COMMENT("effective nop elided");
-          return;
-        }
-        code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
-        break;
-      case lir_div:
-        assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
-        if (c == 1) {
-          // move lreg_lo to dreg if divisor is 1
-          __ mv(dreg, lreg_lo);
-        } else {
-          unsigned int shift = exact_log2_long(c);
-          // use t0 as intermediate result register
-          __ srai(t0, lreg_lo, 0x3f);
-          if (Assembler::is_simm12(c - 1)) {
-            __ andi(t0, t0, c - 1);
-          } else {
-            __ zero_extend(t0, t0, shift);
-          }
-          __ add(dreg, t0, lreg_lo);
-          __ srai(dreg, dreg, shift);
-        }
-        break;
-      case lir_rem:
-        assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
-        if (c == 1) {
-          // move 0 to dreg if divisor is 1
-          __ mv(dreg, zr);
-        } else {
-          unsigned int shift = exact_log2_long(c);
-          __ srai(t0, lreg_lo, 0x3f);
-          __ srli(t0, t0, BitsPerLong - shift);
-          __ add(t1, lreg_lo, t0);
-          if (Assembler::is_simm12(c - 1)) {
-            __ andi(t1, t1, c - 1);
-          } else {
-            __ zero_extend(t1, t1, shift);
-          }
-          __ sub(dreg, t1, t0);
-        }
-        break;
-      default:
-        ShouldNotReachHere();
-    }
-  } else {
-    ShouldNotReachHere();
-  }
-}
-
-void LIR_Assembler::arith_op_single_fpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
-  assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
-  switch (code) {
-    case lir_add: __ fadd_s(dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
-    case lir_sub: __ fsub_s(dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
-    case lir_mul: __ fmul_s(dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
-    case lir_div: __ fdiv_s(dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
-    default:
-      ShouldNotReachHere();
-  }
-}
-
-void LIR_Assembler::arith_op_double_fpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
-  if (right->is_double_fpu()) {
-    // fpu register - fpu register
-    switch (code) {
-      case lir_add: __ fadd_d(dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
-      case lir_sub: __ fsub_d(dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
-      case lir_mul: __ fmul_d(dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
-      case lir_div: __ fdiv_d(dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
-      default:
-        ShouldNotReachHere();
-    }
-  } else {
-    ShouldNotReachHere();
-  }
-}
-
-void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
-                             CodeEmitInfo* info, bool pop_fpu_stack) {
-  assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
-
-  if (left->is_single_cpu()) {
-    arith_op_single_cpu(code, left, right, dest);
-  } else if (left->is_double_cpu()) {
-    arith_op_double_cpu(code, left, right, dest);
-  } else if (left->is_single_fpu()) {
-    arith_op_single_fpu(code, left, right, dest);
-  } else if (left->is_double_fpu()) {
-    arith_op_double_fpu(code, left, right, dest);
-  } else {
-    ShouldNotReachHere();
-  }
-}
-
-#undef __

src/hotspot/cpu/riscv/c1_LIRAssembler_arith_riscv.hpp

@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_LIRASSEMBLER_ARITH_RISCV_HPP
-#define CPU_RISCV_C1_LIRASSEMBLER_ARITH_RISCV_HPP
-
-  // arith_op sub functions
-  void arith_op_single_cpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
-  void arith_op_double_cpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
-  void arith_op_single_fpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
-  void arith_op_double_fpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
-  void arith_op_single_cpu_right_constant(LIR_Code code, LIR_Opr left, LIR_Opr right, Register lreg, Register dreg);
-  void arithmetic_idiv(LIR_Op3* op, bool is_irem);
-
-#endif // CPU_RISCV_C1_LIRASSEMBLER_ARITH_RISCV_HPP

src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.cpp

@@ -1,387 +0,0 @@
-/*
- * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "asm/assembler.hpp"
-#include "c1/c1_LIRAssembler.hpp"
-#include "c1/c1_MacroAssembler.hpp"
-#include "ci/ciArrayKlass.hpp"
-#include "oops/objArrayKlass.hpp"
-#include "runtime/stubRoutines.hpp"
-
-#define __ _masm->
-
-
-void LIR_Assembler::generic_arraycopy(Register src, Register src_pos, Register length,
-                                      Register dst, Register dst_pos, CodeStub *stub) {
-  assert(src == x11 && src_pos == x12, "mismatch in calling convention");
-  // Save the arguments in case the generic arraycopy fails and we
-  // have to fall back to the JNI stub
-  arraycopy_store_args(src, src_pos, length, dst, dst_pos);
-
-  address copyfunc_addr = StubRoutines::generic_arraycopy();
-  assert(copyfunc_addr != NULL, "generic arraycopy stub required");
-
-  // The arguments are in java calling convention so we shift them
-  // to C convention
-  assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
-  __ mv(c_rarg0, j_rarg0);
-  assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
-  __ mv(c_rarg1, j_rarg1);
-  assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
-  __ mv(c_rarg2, j_rarg2);
-  assert_different_registers(c_rarg3, j_rarg4);
-  __ mv(c_rarg3, j_rarg3);
-  __ mv(c_rarg4, j_rarg4);
-#ifndef PRODUCT
-  if (PrintC1Statistics) {
-    __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
-  }
-#endif
-  __ far_call(RuntimeAddress(copyfunc_addr));
-  __ beqz(x10, *stub->continuation());
-  // Reload values from the stack so they are where the stub
-  // expects them.
-  arraycopy_load_args(src, src_pos, length, dst, dst_pos);
-
-  // x10 is -1^K where K == partial copied count
-  __ xori(t0, x10, -1);
-  // adjust length down and src/end pos up by partial copied count
-  __ subw(length, length, t0);
-  __ addw(src_pos, src_pos, t0);
-  __ addw(dst_pos, dst_pos, t0);
-  __ j(*stub->entry());
-
-  __ bind(*stub->continuation());
-}
-
-void LIR_Assembler::arraycopy_simple_check(Register src, Register src_pos, Register length,
-                                           Register dst, Register dst_pos, Register tmp,
-                                           CodeStub *stub, int flags) {
-  // test for NULL
-  if (flags & LIR_OpArrayCopy::src_null_check) {
-    __ beqz(src, *stub->entry(), /* is_far */ true);
-  }
-  if (flags & LIR_OpArrayCopy::dst_null_check) {
-    __ beqz(dst, *stub->entry(), /* is_far */ true);
-  }
-
-  // If the compiler was not able to prove that exact type of the source or the destination
-  // of the arraycopy is an array type, check at runtime if the source or the destination is
-  // an instance type.
-  if (flags & LIR_OpArrayCopy::type_check) {
-    assert(Klass::_lh_neutral_value == 0, "or replace bgez instructions");
-    if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
-      __ load_klass(tmp, dst);
-      __ lw(t0, Address(tmp, in_bytes(Klass::layout_helper_offset())));
-      __ bgez(t0, *stub->entry(), /* is_far */ true);
-    }
-
-    if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
-      __ load_klass(tmp, src);
-      __ lw(t0, Address(tmp, in_bytes(Klass::layout_helper_offset())));
-      __ bgez(t0, *stub->entry(), /* is_far */ true);
-    }
-  }
-
-  // check if negative
-  if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
-    __ bltz(src_pos, *stub->entry(), /* is_far */ true);
-  }
-  if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
-    __ bltz(dst_pos, *stub->entry(), /* is_far */ true);
-  }
-  if (flags & LIR_OpArrayCopy::length_positive_check) {
-    __ bltz(length, *stub->entry(), /* is_far */ true);
-  }
-
-  if (flags & LIR_OpArrayCopy::src_range_check) {
-    __ addw(tmp, src_pos, length);
-    __ lwu(t0, Address(src, arrayOopDesc::length_offset_in_bytes()));
-    __ bgtu(tmp, t0, *stub->entry(), /* is_far */ true);
-  }
-  if (flags & LIR_OpArrayCopy::dst_range_check) {
-    __ addw(tmp, dst_pos, length);
-    __ lwu(t0, Address(dst, arrayOopDesc::length_offset_in_bytes()));
-    __ bgtu(tmp, t0, *stub->entry(), /* is_far */ true);
-  }
-}
-
-void LIR_Assembler::arraycopy_checkcast(Register src, Register src_pos, Register length,
-                                        Register dst, Register dst_pos, Register tmp,
-                                        CodeStub *stub, BasicType basic_type,
-                                        address copyfunc_addr, int flags) {
-  // src is not a sub class of dst so we have to do a
-  // per-element check.
-  int mask = LIR_OpArrayCopy::src_objarray | LIR_OpArrayCopy::dst_objarray;
-  if ((flags & mask) != mask) {
-    // Check that at least both of them object arrays.
-    assert(flags & mask, "one of the two should be known to be an object array");
-
-    if (!(flags & LIR_OpArrayCopy::src_objarray)) {
-      __ load_klass(tmp, src);
-    } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
-      __ load_klass(tmp, dst);
-    }
-    int lh_offset = in_bytes(Klass::layout_helper_offset());
-    Address klass_lh_addr(tmp, lh_offset);
-    jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
-    __ lw(t0, klass_lh_addr);
-    __ mv(t1, objArray_lh);
-    __ bne(t0, t1, *stub->entry(), /* is_far */ true);
-  }
-
-  // Spill because stubs can use any register they like and it's
-  // easier to restore just those that we care about.
-  arraycopy_store_args(src, src_pos, length, dst, dst_pos);
-  arraycopy_checkcast_prepare_params(src, src_pos, length, dst, dst_pos, basic_type);
-  __ far_call(RuntimeAddress(copyfunc_addr));
-
-#ifndef PRODUCT
-  if (PrintC1Statistics) {
-    Label failed;
-    __ bnez(x10, failed);
-    __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
-    __ bind(failed);
-  }
-#endif
-
-  __ beqz(x10, *stub->continuation());
-
-#ifndef PRODUCT
-  if (PrintC1Statistics) {
-    __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
-  }
-#endif
-  assert_different_registers(dst, dst_pos, length, src_pos, src, x10, t0);
-
-  // Restore previously spilled arguments
-  arraycopy_load_args(src, src_pos, length, dst, dst_pos);
-
-  // return value is -1^K where K is partial copied count
-  __ xori(t0, x10, -1);
-  // adjust length down and src/end pos up by partial copied count
-  __ subw(length, length, t0);
-  __ addw(src_pos, src_pos, t0);
-  __ addw(dst_pos, dst_pos, t0);
-}
-
-void LIR_Assembler::arraycopy_type_check(Register src, Register src_pos, Register length,
-                                         Register dst, Register dst_pos, Register tmp,
-                                         CodeStub *stub, BasicType basic_type, int flags) {
-  // We don't know the array types are compatible
-  if (basic_type != T_OBJECT) {
-    // Simple test for basic type arrays
-    if (UseCompressedClassPointers) {
-      __ lwu(tmp, Address(src, oopDesc::klass_offset_in_bytes()));
-      __ lwu(t0, Address(dst, oopDesc::klass_offset_in_bytes()));
-    } else {
-      __ ld(tmp, Address(src, oopDesc::klass_offset_in_bytes()));
-      __ ld(t0, Address(dst, oopDesc::klass_offset_in_bytes()));
-    }
-    __ bne(tmp, t0, *stub->entry(), /* is_far */ true);
-  } else {
-    // For object arrays, if src is a sub class of dst then we can
-    // safely do the copy.
-    Label cont, slow;
-
-#define PUSH(r1, r2)                                     \
-    __ addi(sp, sp, -2 * wordSize);                      \
-    __ sd(r1, Address(sp, 1 * wordSize));                \
-    __ sd(r2, Address(sp, 0));
-
-#define POP(r1, r2)                                      \
-    __ ld(r1, Address(sp, 1 * wordSize));                \
-    __ ld(r2, Address(sp, 0));                           \
-    __ addi(sp, sp, 2 * wordSize);
-
-    PUSH(src, dst);
-    __ load_klass(src, src);
-    __ load_klass(dst, dst);
-    __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
-
-    PUSH(src, dst);
-    __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
-    POP(src, dst);
-    __ bnez(dst, cont);
-
-    __ bind(slow);
-    POP(src, dst);
-
-    address copyfunc_addr = StubRoutines::checkcast_arraycopy();
-    if (copyfunc_addr != NULL) { // use stub if available
-      arraycopy_checkcast(src, src_pos, length, dst, dst_pos, tmp, stub, basic_type, copyfunc_addr, flags);
-    }
-
-    __ j(*stub->entry());
-    __ bind(cont);
-    POP(src, dst);
-  }
-}
-
-void LIR_Assembler::arraycopy_assert(Register src, Register dst, Register tmp, ciArrayKlass *default_type, int flags) {
-  assert(default_type != NULL, "NULL default_type!");
-  BasicType basic_type = default_type->element_type()->basic_type();
-
-  if (basic_type == T_ARRAY) { basic_type = T_OBJECT; }
-  if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
-    // Sanity check the known type with the incoming class.  For the
-    // primitive case the types must match exactly with src.klass and
-    // dst.klass each exactly matching the default type.  For the
-    // object array case, if no type check is needed then either the
-    // dst type is exactly the expected type and the src type is a
-    // subtype which we can't check or src is the same array as dst
-    // but not necessarily exactly of type default_type.
-    Label known_ok, halt;
-    __ mov_metadata(tmp, default_type->constant_encoding());
-    if (UseCompressedClassPointers) {
-      __ encode_klass_not_null(tmp);
-    }
-
-    if (basic_type != T_OBJECT) {
-      if (UseCompressedClassPointers) {
-        __ lwu(t0, Address(dst, oopDesc::klass_offset_in_bytes()));
-      } else {
-        __ ld(t0, Address(dst, oopDesc::klass_offset_in_bytes()));
-      }
-      __ bne(tmp, t0, halt);
-      if (UseCompressedClassPointers) {
-        __ lwu(t0, Address(src, oopDesc::klass_offset_in_bytes()));
-      } else {
-        __ ld(t0, Address(src, oopDesc::klass_offset_in_bytes()));
-      }
-      __ beq(tmp, t0, known_ok);
-    } else {
-      if (UseCompressedClassPointers) {
-        __ lwu(t0, Address(dst, oopDesc::klass_offset_in_bytes()));
-      } else {
-        __ ld(t0, Address(dst, oopDesc::klass_offset_in_bytes()));
-      }
-      __ beq(tmp, t0, known_ok);
-      __ beq(src, dst, known_ok);
-    }
-    __ bind(halt);
-    __ stop("incorrect type information in arraycopy");
-    __ bind(known_ok);
-  }
-}
-
-void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
-  ciArrayKlass *default_type = op->expected_type();
-  Register src = op->src()->as_register();
-  Register dst = op->dst()->as_register();
-  Register src_pos = op->src_pos()->as_register();
-  Register dst_pos = op->dst_pos()->as_register();
-  Register length = op->length()->as_register();
-  Register tmp = op->tmp()->as_register();
-
-  CodeStub* stub = op->stub();
-  int flags = op->flags();
-  BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
-  if (is_reference_type(basic_type)) { basic_type = T_OBJECT; }
-
-  // if we don't know anything, just go through the generic arraycopy
-  if (default_type == NULL) {
-    generic_arraycopy(src, src_pos, length, dst, dst_pos, stub);
-    return;
-  }
-
-  assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(),
-         "must be true at this point");
-
-  arraycopy_simple_check(src, src_pos, length, dst, dst_pos, tmp, stub, flags);
-
-  if (flags & LIR_OpArrayCopy::type_check) {
-    arraycopy_type_check(src, src_pos, length, dst, dst_pos, tmp, stub, basic_type, flags);
-  }
-
-#ifdef ASSERT
-  arraycopy_assert(src, dst, tmp, default_type, flags);
-#endif
-
-#ifndef PRODUCT
-  if (PrintC1Statistics) {
-    __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
-  }
-#endif
-  arraycopy_prepare_params(src, src_pos, length, dst, dst_pos, basic_type);
-
-  bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
-  bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
-  const char *name = NULL;
-  address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
-
-  CodeBlob *cb = CodeCache::find_blob(entry);
-  if (cb != NULL) {
-    __ far_call(RuntimeAddress(entry));
-  } else {
-    const int args_num = 3;
-    __ call_VM_leaf(entry, args_num);
-  }
-
-  __ bind(*stub->continuation());
-}
-
-
-void LIR_Assembler::arraycopy_prepare_params(Register src, Register src_pos, Register length,
-                                             Register dst, Register dst_pos, BasicType basic_type) {
-  int scale = array_element_size(basic_type);
-  __ shadd(c_rarg0, src_pos, src, t0, scale);
-  __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
-  assert_different_registers(c_rarg0, dst, dst_pos, length);
-  __ shadd(c_rarg1, dst_pos, dst, t0, scale);
-  __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
-  assert_different_registers(c_rarg1, dst, length);
-  __ mv(c_rarg2, length);
-  assert_different_registers(c_rarg2, dst);
-}
-
-void LIR_Assembler::arraycopy_checkcast_prepare_params(Register src, Register src_pos, Register length,
-                                                       Register dst, Register dst_pos, BasicType basic_type) {
-  arraycopy_prepare_params(src, src_pos, length, dst, dst_pos, basic_type);
-  __ load_klass(c_rarg4, dst);
-  __ ld(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
-  __ lwu(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
-}
-
-void LIR_Assembler::arraycopy_store_args(Register src, Register src_pos, Register length,
-                                         Register dst, Register dst_pos) {
-  __ sd(dst_pos, Address(sp, 0));                // 0: dst_pos sp offset
-  __ sd(dst, Address(sp, 1 * BytesPerWord));     // 1: dst sp offset
-  __ sd(length, Address(sp, 2 * BytesPerWord));  // 2: length sp offset
-  __ sd(src_pos, Address(sp, 3 * BytesPerWord)); // 3: src_pos sp offset
-  __ sd(src, Address(sp, 4 * BytesPerWord));     // 4: src sp offset
-}
-
-void LIR_Assembler::arraycopy_load_args(Register src, Register src_pos, Register length,
-                                        Register dst, Register dst_pos) {
-  __ ld(dst_pos, Address(sp, 0));                // 0: dst_pos sp offset
-  __ ld(dst, Address(sp, 1 * BytesPerWord));     // 1: dst sp offset
-  __ ld(length, Address(sp, 2 * BytesPerWord));  // 2: length sp offset
-  __ ld(src_pos, Address(sp, 3 * BytesPerWord)); // 3: src_pos sp offset
-  __ ld(src, Address(sp, 4 * BytesPerWord));     // 4: src sp offset
-}
-
-#undef __

src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.hpp

@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_LIRASSEMBLER_ARRAYCOPY_RISCV_HPP
-#define CPU_RISCV_C1_LIRASSEMBLER_ARRAYCOPY_RISCV_HPP
-
-  // arraycopy sub functions
-  void generic_arraycopy(Register src, Register src_pos, Register length,
-                         Register dst, Register dst_pos, CodeStub *stub);
-  void arraycopy_simple_check(Register src, Register src_pos, Register length,
-                              Register dst, Register dst_pos, Register tmp,
-                              CodeStub *stub, int flags);
-  void arraycopy_checkcast(Register src, Register src_pos, Register length,
-                           Register dst, Register dst_pos, Register tmp,
-                           CodeStub *stub, BasicType basic_type,
-                           address copyfunc_addr, int flags);
-  void arraycopy_type_check(Register src, Register src_pos, Register length,
-                            Register dst, Register dst_pos, Register tmp,
-                            CodeStub *stub, BasicType basic_type, int flags);
-  void arraycopy_assert(Register src, Register dst, Register tmp, ciArrayKlass *default_type, int flags);
-  void arraycopy_prepare_params(Register src, Register src_pos, Register length,
-                                Register dst, Register dst_pos, BasicType basic_type);
-  void arraycopy_checkcast_prepare_params(Register src, Register src_pos, Register length,
-                                          Register dst, Register dst_pos, BasicType basic_type);
-  void arraycopy_store_args(Register src, Register src_pos, Register length,
-                            Register dst, Register dst_pos);
-  void arraycopy_load_args(Register src, Register src_pos, Register length,
-                           Register dst, Register dst_pos);
-
-#endif // CPU_RISCV_C1_LIRASSEMBLER_ARRAYCOPY_RISCV_HPP

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp

@@ -1,130 +0,0 @@
-/*
- * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_LIRASSEMBLER_RISCV_HPP
-#define CPU_RISCV_C1_LIRASSEMBLER_RISCV_HPP
-
-// ArrayCopyStub needs access to bailout
-friend class ArrayCopyStub;
-
-private:
-
-#include "c1_LIRAssembler_arith_riscv.hpp"
-#include "c1_LIRAssembler_arraycopy_riscv.hpp"
-
-  int array_element_size(BasicType type) const;
-
-  static Register as_reg(LIR_Opr op) {
-    return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
-  }
-
-  Address as_Address(LIR_Address* addr, Register tmp);
-
-  // helper functions which checks for overflow and sets bailout if it
-  // occurs.  Always returns a valid embeddable pointer but in the
-  // bailout case the pointer won't be to unique storage.
-  address float_constant(float f);
-  address double_constant(double d);
-  address int_constant(jlong n);
-
-  // Ensure we have a valid Address (base + offset) to a stack-slot.
-  Address stack_slot_address(int index, uint shift, int adjust = 0);
-
-  // Record the type of the receiver in ReceiverTypeData
-  void type_profile_helper(Register mdo,
-                           ciMethodData *md, ciProfileData *data,
-                           Register recv, Label* update_done);
-
-  void casw(Register addr, Register newval, Register cmpval);
-  void caswu(Register addr, Register newval, Register cmpval);
-  void casl(Register addr, Register newval, Register cmpval);
-
-  void poll_for_safepoint(relocInfo::relocType rtype, CodeEmitInfo* info = NULL);
-
-  void deoptimize_trap(CodeEmitInfo *info);
-
-  enum {
-    // See emit_static_call_stub for detail
-    // CompiledStaticCall::to_interp_stub_size() (14) + CompiledStaticCall::to_trampoline_stub_size() (1 + 3 + address)
-    _call_stub_size = 14 * NativeInstruction::instruction_size +
-                      (NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size),
-    // See emit_exception_handler for detail
-    // verify_not_null_oop + far_call + should_not_reach_here + invalidate_registers(DEBUG_ONLY)
-    _exception_handler_size = DEBUG_ONLY(584) NOT_DEBUG(548), // or smaller
-    // See emit_deopt_handler for detail
-    // auipc (1) + far_jump (6 or 2)
-    _deopt_handler_size = 1 * NativeInstruction::instruction_size +
-                          6 * NativeInstruction::instruction_size // or smaller
-  };
-
-  void check_conflict(ciKlass* exact_klass, intptr_t current_klass, Register tmp,
-                      Label &next, Label &none, Address mdo_addr);
-  void check_no_conflict(ciKlass* exact_klass, intptr_t current_klass, Register tmp, Address mdo_addr, Label &next);
-
-  void check_exact_klass(Register tmp, ciKlass* exact_klass);
-
-  void check_null(Register tmp, Label &update, intptr_t current_klass, Address mdo_addr, bool do_update, Label &next);
-
-  void (MacroAssembler::*add)(Register prev, RegisterOrConstant incr, Register addr);
-  void (MacroAssembler::*xchg)(Register prev, Register newv, Register addr);
-
-  void get_op(BasicType type);
-
-  // emit_typecheck_helper sub functions
-  void data_check(LIR_OpTypeCheck *op, ciMethodData **md, ciProfileData **data);
-  void typecheck_helper_slowcheck(ciKlass* k, Register obj, Register Rtmp1,
-                                  Register k_RInfo, Register klass_RInfo,
-                                  Label* failure_target, Label* success_target);
-  void profile_object(ciMethodData* md, ciProfileData* data, Register obj,
-                      Register klass_RInfo, Label* obj_is_null);
-  void typecheck_loaded(LIR_OpTypeCheck* op, ciKlass* k, Register k_RInfo);
-
-  // emit_opTypeCheck sub functions
-  void typecheck_lir_store(LIR_OpTypeCheck* op, bool should_profile);
-
-  void type_profile(Register obj, ciMethodData* md, Register klass_RInfo, Register k_RInfo,
-                    ciProfileData* data, Label* success, Label* failure,
-                    Label& profile_cast_success, Label& profile_cast_failure);
-
-  void lir_store_slowcheck(Register k_RInfo, Register klass_RInfo, Register Rtmp1,
-                           Label* success_target, Label* failure_target);
-
-  void const2reg_helper(LIR_Opr src);
-
-  void emit_branch(LIR_Condition cmp_flag, LIR_Opr cmp1, LIR_Opr cmp2, Label& label, bool is_far, bool is_unordered);
-
-  void logic_op_reg32(Register dst, Register left, Register right, LIR_Code code);
-  void logic_op_reg(Register dst, Register left, Register right, LIR_Code code);
-  void logic_op_imm(Register dst, Register left, int right, LIR_Code code);
-
-public:
-
-  void emit_cmove(LIR_Op4* op);
-
-  void store_parameter(Register r, int offset_from_rsp_in_words);
-  void store_parameter(jint c, int offset_from_rsp_in_words);
-
-#endif // CPU_RISCV_C1_LIRASSEMBLER_RISCV_HPP

src/hotspot/cpu/riscv/c1_LIR_riscv.cpp

@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2016, 2020, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "asm/register.hpp"
-#include "c1/c1_LIR.hpp"
-
-FloatRegister LIR_OprDesc::as_float_reg() const {
-  return as_FloatRegister(fpu_regnr());
-}
-
-FloatRegister LIR_OprDesc::as_double_reg() const {
-  return as_FloatRegister(fpu_regnrLo());
-}
-
-// Reg2 unused.
-LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
-  assert(as_FloatRegister(reg2) == fnoreg, "Not used on this platform");
-  return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
-                             (reg1 << LIR_OprDesc::reg2_shift) |
-                             LIR_OprDesc::double_type          |
-                             LIR_OprDesc::fpu_register         |
-                             LIR_OprDesc::double_size);
-}
-
-#ifndef PRODUCT
-void LIR_Address::verify() const {
-  assert(base()->is_cpu_register(), "wrong base operand");
-  assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
-  assert(base()->type() == T_ADDRESS || base()->type() == T_OBJECT || base()->type() == T_LONG ||
-         base()->type() == T_METADATA, "wrong type for addresses");
-}
-#endif // PRODUCT

src/hotspot/cpu/riscv/c1_LinearScan_riscv.cpp

@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "c1/c1_Instruction.hpp"
-#include "c1/c1_LinearScan.hpp"
-#include "utilities/bitMap.inline.hpp"
-
-void LinearScan::allocate_fpu_stack() {
-  // No FPU stack on RISCV
-}

src/hotspot/cpu/riscv/c1_LinearScan_riscv.hpp

@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_LINEARSCAN_RISCV_HPP
-#define CPU_RISCV_C1_LINEARSCAN_RISCV_HPP
-
-inline bool LinearScan::is_processed_reg_num(int reg_num)
-{
-  return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map;
-}
-
-inline int LinearScan::num_physical_regs(BasicType type) {
-  return 1;
-}
-
-inline bool LinearScan::requires_adjacent_regs(BasicType type) {
-  return false;
-}
-
-inline bool LinearScan::is_caller_save(int assigned_reg) {
-  assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
-  if (assigned_reg < pd_first_callee_saved_reg) {
-    return true;
-  }
-  if (assigned_reg > pd_last_callee_saved_reg && assigned_reg < pd_first_callee_saved_fpu_reg_1) {
-    return true;
-  }
-  if (assigned_reg > pd_last_callee_saved_fpu_reg_1 && assigned_reg < pd_first_callee_saved_fpu_reg_2) {
-    return true;
-  }
-  if (assigned_reg > pd_last_callee_saved_fpu_reg_2 && assigned_reg < pd_last_fpu_reg) {
-    return true;
-  }
-  return false;
-}
-
-inline void LinearScan::pd_add_temps(LIR_Op* op) {
-  // No special case behaviours yet
-}
-
-
-// Implementation of LinearScanWalker
-
-inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur)
-{
-  if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) {
-    assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
-    _first_reg = pd_first_callee_saved_reg;
-    _last_reg = pd_last_callee_saved_reg;
-    return true;
-  } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT ||
-             cur->type() == T_ADDRESS || cur->type() == T_METADATA) {
-    _first_reg = pd_first_cpu_reg;
-    _last_reg = pd_last_allocatable_cpu_reg;
-    return true;
-  }
-  return false;
-}
-
-#endif // CPU_RISCV_C1_LINEARSCAN_RISCV_HPP

src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp

@@ -1,451 +0,0 @@
-/*
- * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "c1/c1_LIR.hpp"
-#include "c1/c1_MacroAssembler.hpp"
-#include "c1/c1_Runtime1.hpp"
-#include "classfile/systemDictionary.hpp"
-#include "gc/shared/barrierSetAssembler.hpp"
-#include "gc/shared/collectedHeap.hpp"
-#include "interpreter/interpreter.hpp"
-#include "oops/arrayOop.hpp"
-#include "oops/markWord.hpp"
-#include "runtime/basicLock.hpp"
-#include "runtime/os.hpp"
-#include "runtime/sharedRuntime.hpp"
-#include "runtime/stubRoutines.hpp"
-
-void C1_MacroAssembler::float_cmp(bool is_float, int unordered_result,
-                                  FloatRegister freg0, FloatRegister freg1,
-                                  Register result) {
-  if (is_float) {
-    float_compare(result, freg0, freg1, unordered_result);
-  } else {
-    double_compare(result, freg0, freg1, unordered_result);
-  }
-}
-
-int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr, Register tmp, Label& slow_case) {
-  const int aligned_mask = BytesPerWord - 1;
-  const int hdr_offset = oopDesc::mark_offset_in_bytes();
-  assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
-  Label done;
-  int null_check_offset = -1;
-
-  verify_oop(obj);
-
-  // save object being locked into the BasicObjectLock
-  sd(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
-
-  null_check_offset = offset();
-
-  if (DiagnoseSyncOnValueBasedClasses != 0) {
-    load_klass(hdr, obj);
-    lwu(hdr, Address(hdr, Klass::access_flags_offset()));
-    test_bit(t0, hdr, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS));
-    bnez(t0, slow_case, true /* is_far */);
-  }
-
-  if (UseBiasedLocking) {
-    assert(tmp != noreg, "should have tmp register at this point");
-    biased_locking_enter(disp_hdr, obj, hdr, tmp, false, done, &slow_case);
-  }
-
-  // Load object header
-  ld(hdr, Address(obj, hdr_offset));
-  // and mark it as unlocked
-  ori(hdr, hdr, markWord::unlocked_value);
-  // save unlocked object header into the displaced header location on the stack
-  sd(hdr, Address(disp_hdr, 0));
-  // test if object header is still the same (i.e. unlocked), and if so, store the
-  // displaced header address in the object header - if it is not the same, get the
-  // object header instead
-  la(t1, Address(obj, hdr_offset));
-  cmpxchgptr(hdr, disp_hdr, t1, t0, done, /*fallthough*/NULL);
-  // if the object header was the same, we're done
-  // if the object header was not the same, it is now in the hdr register
-  // => test if it is a stack pointer into the same stack (recursive locking), i.e.:
-  //
-  // 1) (hdr & aligned_mask) == 0
-  // 2) sp <= hdr
-  // 3) hdr <= sp + page_size
-  //
-  // these 3 tests can be done by evaluating the following expression:
-  //
-  // (hdr -sp) & (aligned_mask - page_size)
-  //
-  // assuming both the stack pointer and page_size have their least
-  // significant 2 bits cleared and page_size is a power of 2
-  sub(hdr, hdr, sp);
-  mv(t0, aligned_mask - os::vm_page_size());
-  andr(hdr, hdr, t0);
-  // for recursive locking, the result is zero => save it in the displaced header
-  // location (NULL in the displaced hdr location indicates recursive locking)
-  sd(hdr, Address(disp_hdr, 0));
-  // otherwise we don't care about the result and handle locking via runtime call
-  bnez(hdr, slow_case, /* is_far */ true);
-  bind(done);
-  return null_check_offset;
-}
-
-void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_hdr, Label& slow_case) {
-  const int aligned_mask = BytesPerWord - 1;
-  const int hdr_offset = oopDesc::mark_offset_in_bytes();
-  assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
-  Label done;
-
-  if (UseBiasedLocking) {
-    // load object
-    ld(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
-    biased_locking_exit(obj, hdr, done);
-  }
-
-  // load displaced header
-  ld(hdr, Address(disp_hdr, 0));
-  // if the loaded hdr is NULL we had recursive locking
-  // if we had recursive locking, we are done
-  beqz(hdr, done);
-  if (!UseBiasedLocking) {
-    // load object
-    ld(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
-  }
-  verify_oop(obj);
-  // test if object header is pointing to the displaced header, and if so, restore
-  // the displaced header in the object - if the object header is not pointing to
-  // the displaced header, get the object header instead
-  // if the object header was not pointing to the displaced header,
-  // we do unlocking via runtime call
-  if (hdr_offset) {
-    la(t0, Address(obj, hdr_offset));
-    cmpxchgptr(disp_hdr, hdr, t0, t1, done, &slow_case);
-  } else {
-    cmpxchgptr(disp_hdr, hdr, obj, t1, done, &slow_case);
-  }
-  bind(done);
-}
-
-// Defines obj, preserves var_size_in_bytes
-void C1_MacroAssembler::try_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes, Register tmp1, Register tmp2, Label& slow_case) {
-  if (UseTLAB) {
-    tlab_allocate(obj, var_size_in_bytes, con_size_in_bytes, tmp1, tmp2, slow_case, /* is_far */ true);
-  } else {
-    eden_allocate(obj, var_size_in_bytes, con_size_in_bytes, tmp1, slow_case, /* is_far */ true);
-  }
-}
-
-void C1_MacroAssembler::initialize_header(Register obj, Register klass, Register len, Register tmp1, Register tmp2) {
-  assert_different_registers(obj, klass, len);
-  if (UseBiasedLocking & !len->is_valid()) {
-    assert_different_registers(obj, klass, len, tmp1, tmp2);
-    ld(tmp1, Address(klass, Klass::prototype_header_offset()));
-  } else {
-    // This assumes that all prototype bits fitr in an int32_t
-    mv(tmp1, (int32_t)(intptr_t)markWord::prototype().value());
-  }
-  sd(tmp1, Address(obj, oopDesc::mark_offset_in_bytes()));
-
-  if (UseCompressedClassPointers) { // Take care not to kill klass
-    encode_klass_not_null(tmp1, klass, tmp2);
-    sw(tmp1, Address(obj, oopDesc::klass_offset_in_bytes()));
-  } else {
-    sd(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
-  }
-
-  if (len->is_valid()) {
-    sw(len, Address(obj, arrayOopDesc::length_offset_in_bytes()));
-  } else if (UseCompressedClassPointers) {
-    store_klass_gap(obj, zr);
-  }
-}
-
-// preserves obj, destroys len_in_bytes
-void C1_MacroAssembler::initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register tmp) {
-  assert(hdr_size_in_bytes >= 0, "header size must be positive or 0");
-  Label done;
-
-  // len_in_bytes is positive and ptr sized
-  sub(len_in_bytes, len_in_bytes, hdr_size_in_bytes);
-  beqz(len_in_bytes, done);
-
-  // Preserve obj
-  if (hdr_size_in_bytes) {
-    add(obj, obj, hdr_size_in_bytes);
-  }
-  zero_memory(obj, len_in_bytes, tmp);
-  if (hdr_size_in_bytes) {
-    sub(obj, obj, hdr_size_in_bytes);
-  }
-
-  bind(done);
-}
-
-void C1_MacroAssembler::allocate_object(Register obj, Register tmp1, Register tmp2, int header_size, int object_size, Register klass, Label& slow_case) {
-  assert_different_registers(obj, tmp1, tmp2);
-  assert(header_size >= 0 && object_size >= header_size, "illegal sizes");
-
-  try_allocate(obj, noreg, object_size * BytesPerWord, tmp1, tmp2, slow_case);
-
-  initialize_object(obj, klass, noreg, object_size * HeapWordSize, tmp1, tmp2, UseTLAB);
-}
-
-void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register var_size_in_bytes, int con_size_in_bytes, Register tmp1, Register tmp2, bool is_tlab_allocated) {
-  assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0,
-         "con_size_in_bytes is not multiple of alignment");
-  const int hdr_size_in_bytes = instanceOopDesc::header_size() * HeapWordSize;
-
-  initialize_header(obj, klass, noreg, tmp1, tmp2);
-
-  if (!(UseTLAB && ZeroTLAB && is_tlab_allocated)) {
-    // clear rest of allocated space
-    const Register index = tmp2;
-    // 16: multipler for threshold
-    const int threshold = 16 * BytesPerWord;    // approximate break even point for code size (see comments below)
-    if (var_size_in_bytes != noreg) {
-      mv(index, var_size_in_bytes);
-      initialize_body(obj, index, hdr_size_in_bytes, tmp1);
-    } else if (con_size_in_bytes <= threshold) {
-      // use explicit null stores
-      int i = hdr_size_in_bytes;
-      if (i < con_size_in_bytes && (con_size_in_bytes % (2 * BytesPerWord))) { // 2: multipler for BytesPerWord
-        sd(zr, Address(obj, i));
-        i += BytesPerWord;
-      }
-      for (; i < con_size_in_bytes; i += BytesPerWord) {
-        sd(zr, Address(obj, i));
-      }
-    } else if (con_size_in_bytes > hdr_size_in_bytes) {
-      block_comment("zero memory");
-      // use loop to null out the fields
-      int words = (con_size_in_bytes - hdr_size_in_bytes) / BytesPerWord;
-      mv(index, words / 8); // 8: byte size
-
-      const int unroll = 8; // Number of sd(zr) instructions we'll unroll
-      int remainder = words % unroll;
-      la(t0, Address(obj, hdr_size_in_bytes + remainder * BytesPerWord));
-
-      Label entry_point, loop;
-      j(entry_point);
-
-      bind(loop);
-      sub(index, index, 1);
-      for (int i = -unroll; i < 0; i++) {
-        if (-i == remainder) {
-          bind(entry_point);
-        }
-        sd(zr, Address(t0, i * wordSize));
-      }
-      if (remainder == 0) {
-        bind(entry_point);
-      }
-      add(t0, t0, unroll * wordSize);
-      bnez(index, loop);
-    }
-  }
-
-  membar(MacroAssembler::StoreStore);
-
-  if (CURRENT_ENV->dtrace_alloc_probes()) {
-    assert(obj == x10, "must be");
-    far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::dtrace_object_alloc_id)));
-  }
-
-  verify_oop(obj);
-}
-
-void C1_MacroAssembler::allocate_array(Register obj, Register len, Register tmp1, Register tmp2, int header_size, int f, Register klass, Label& slow_case) {
-  assert_different_registers(obj, len, tmp1, tmp2, klass);
-
-  // determine alignment mask
-  assert(!(BytesPerWord & 1), "must be multiple of 2 for masking code to work");
-
-  // check for negative or excessive length
-  mv(t0, (int32_t)max_array_allocation_length);
-  bgeu(len, t0, slow_case, /* is_far */ true);
-
-  const Register arr_size = tmp2; // okay to be the same
-  // align object end
-  mv(arr_size, (int32_t)header_size * BytesPerWord + MinObjAlignmentInBytesMask);
-  shadd(arr_size, len, arr_size, t0, f);
-  andi(arr_size, arr_size, ~(uint)MinObjAlignmentInBytesMask);
-
-  try_allocate(obj, arr_size, 0, tmp1, tmp2, slow_case);
-
-  initialize_header(obj, klass, len, tmp1, tmp2);
-
-  // clear rest of allocated space
-  const Register len_zero = len;
-  initialize_body(obj, arr_size, header_size * BytesPerWord, len_zero);
-
-  membar(MacroAssembler::StoreStore);
-
-  if (CURRENT_ENV->dtrace_alloc_probes()) {
-    assert(obj == x10, "must be");
-    far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::dtrace_object_alloc_id)));
-  }
-
-  verify_oop(obj);
-}
-
-void C1_MacroAssembler::inline_cache_check(Register receiver, Register iCache, Label &L) {
-  verify_oop(receiver);
-  // explicit NULL check not needed since load from [klass_offset] causes a trap
-  // check against inline cache
-  assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), "must add explicit null check");
-  assert_different_registers(receiver, iCache, t0, t2);
-  cmp_klass(receiver, iCache, t0, t2 /* call-clobbered t2 as a tmp */, L);
-}
-
-void C1_MacroAssembler::build_frame(int framesize, int bang_size_in_bytes) {
-  assert(bang_size_in_bytes >= framesize, "stack bang size incorrect");
-  // Make sure there is enough stack space for this method's activation.
-  // Note that we do this before creating a frame.
-  generate_stack_overflow_check(bang_size_in_bytes);
-  MacroAssembler::build_frame(framesize);
-
-  // Insert nmethod entry barrier into frame.
-  BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
-  bs->nmethod_entry_barrier(this);
-}
-
-void C1_MacroAssembler::remove_frame(int framesize) {
-  MacroAssembler::remove_frame(framesize);
-}
-
-
-void C1_MacroAssembler::verified_entry(bool breakAtEntry) {
-  // If we have to make this method not-entrant we'll overwrite its
-  // first instruction with a jump. For this action to be legal we
-  // must ensure that this first instruction is a J, JAL or NOP.
-  // Make it a NOP.
-  IncompressibleRegion ir(this);  // keep the nop as 4 bytes for patching.
-  assert_alignment(pc());
-  nop();  // 4 bytes
-}
-
-void C1_MacroAssembler::load_parameter(int offset_in_words, Register reg) {
-  //  fp + -2: link
-  //     + -1: return address
-  //     +  0: argument with offset 0
-  //     +  1: argument with offset 1
-  //     +  2: ...
-  ld(reg, Address(fp, offset_in_words * BytesPerWord));
-}
-
-#ifndef PRODUCT
-
-void C1_MacroAssembler::verify_stack_oop(int stack_offset) {
-  if (!VerifyOops) {
-    return;
-  }
-  verify_oop_addr(Address(sp, stack_offset), "oop");
-}
-
-void C1_MacroAssembler::verify_not_null_oop(Register r) {
-  if (!VerifyOops) return;
-  Label not_null;
-  bnez(r, not_null);
-  stop("non-null oop required");
-  bind(not_null);
-  verify_oop(r);
-}
-
-void C1_MacroAssembler::invalidate_registers(bool inv_x10, bool inv_x9, bool inv_x12, bool inv_x13, bool inv_x14, bool inv_x15) {
-#ifdef ASSERT
-  static int nn;
-  if (inv_x10) { mv(x10, 0xDEAD); }
-  if (inv_x9)  { mv(x9, 0xDEAD);  }
-  if (inv_x12) { mv(x12, nn++);   }
-  if (inv_x13) { mv(x13, 0xDEAD); }
-  if (inv_x14) { mv(x14, 0xDEAD); }
-  if (inv_x15) { mv(x15, 0xDEAD); }
-#endif // ASSERT
-}
-#endif // ifndef PRODUCT
-
-typedef void (C1_MacroAssembler::*c1_cond_branch_insn)(Register op1, Register op2, Label& label, bool is_far);
-typedef void (C1_MacroAssembler::*c1_float_cond_branch_insn)(FloatRegister op1, FloatRegister op2,
-              Label& label, bool is_far, bool is_unordered);
-
-static c1_cond_branch_insn c1_cond_branch[] =
-{
-  /* SHORT branches */
-  (c1_cond_branch_insn)&MacroAssembler::beq,
-  (c1_cond_branch_insn)&MacroAssembler::bne,
-  (c1_cond_branch_insn)&MacroAssembler::blt,
-  (c1_cond_branch_insn)&MacroAssembler::ble,
-  (c1_cond_branch_insn)&MacroAssembler::bge,
-  (c1_cond_branch_insn)&MacroAssembler::bgt,
-  (c1_cond_branch_insn)&MacroAssembler::bleu, // lir_cond_belowEqual
-  (c1_cond_branch_insn)&MacroAssembler::bgeu  // lir_cond_aboveEqual
-};
-
-static c1_float_cond_branch_insn c1_float_cond_branch[] =
-{
-  /* FLOAT branches */
-  (c1_float_cond_branch_insn)&MacroAssembler::float_beq,
-  (c1_float_cond_branch_insn)&MacroAssembler::float_bne,
-  (c1_float_cond_branch_insn)&MacroAssembler::float_blt,
-  (c1_float_cond_branch_insn)&MacroAssembler::float_ble,
-  (c1_float_cond_branch_insn)&MacroAssembler::float_bge,
-  (c1_float_cond_branch_insn)&MacroAssembler::float_bgt,
-  NULL, // lir_cond_belowEqual
-  NULL, // lir_cond_aboveEqual
-
-  /* DOUBLE branches */
-  (c1_float_cond_branch_insn)&MacroAssembler::double_beq,
-  (c1_float_cond_branch_insn)&MacroAssembler::double_bne,
-  (c1_float_cond_branch_insn)&MacroAssembler::double_blt,
-  (c1_float_cond_branch_insn)&MacroAssembler::double_ble,
-  (c1_float_cond_branch_insn)&MacroAssembler::double_bge,
-  (c1_float_cond_branch_insn)&MacroAssembler::double_bgt,
-  NULL, // lir_cond_belowEqual
-  NULL  // lir_cond_aboveEqual
-};
-
-void C1_MacroAssembler::c1_cmp_branch(int cmpFlag, Register op1, Register op2, Label& label,
-                                      BasicType type, bool is_far) {
-  if (type == T_OBJECT || type == T_ARRAY) {
-    assert(cmpFlag == lir_cond_equal || cmpFlag == lir_cond_notEqual, "Should be equal or notEqual");
-    if (cmpFlag == lir_cond_equal) {
-      beq(op1, op2, label, is_far);
-    } else {
-      bne(op1, op2, label, is_far);
-    }
-  } else {
-    assert(cmpFlag >= 0 && cmpFlag < (int)(sizeof(c1_cond_branch) / sizeof(c1_cond_branch[0])),
-           "invalid c1 conditional branch index");
-    (this->*c1_cond_branch[cmpFlag])(op1, op2, label, is_far);
-  }
-}
-
-void C1_MacroAssembler::c1_float_cmp_branch(int cmpFlag, FloatRegister op1, FloatRegister op2, Label& label,
-                                            bool is_far, bool is_unordered) {
-  assert(cmpFlag >= 0 &&
-         cmpFlag < (int)(sizeof(c1_float_cond_branch) / sizeof(c1_float_cond_branch[0])),
-         "invalid c1 float conditional branch index");
-  (this->*c1_float_cond_branch[cmpFlag])(op1, op2, label, is_far, is_unordered);
-}

src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.hpp

@@ -1,121 +0,0 @@
-/*
- * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_MACROASSEMBLER_RISCV_HPP
-#define CPU_RISCV_C1_MACROASSEMBLER_RISCV_HPP
-
-using MacroAssembler::build_frame;
-using MacroAssembler::null_check;
-
-// C1_MacroAssembler contains high-level macros for C1
-
- private:
-  int _rsp_offset;    // track rsp changes
-  // initialization
-  void pd_init() { _rsp_offset = 0; }
-
-
- public:
-  void try_allocate(
-    Register obj,                      // result: pointer to object after successful allocation
-    Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
-    int      con_size_in_bytes,        // object size in bytes if known at compile time
-    Register tmp1,                     // temp register
-    Register tmp2,                     // temp register
-    Label&   slow_case                 // continuation point if fast allocation fails
-  );
-
-  void initialize_header(Register obj, Register klass, Register len, Register tmp1, Register tmp2);
-  void initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register tmp);
-
-  void float_cmp(bool is_float, int unordered_result,
-                 FloatRegister f0, FloatRegister f1,
-                 Register result);
-
-  // locking
-  // hdr     : must be x10, contents destroyed
-  // obj     : must point to the object to lock, contents preserved
-  // disp_hdr: must point to the displaced header location, contents preserved
-  // tmp     : temporary register, contents destroyed
-  // returns code offset at which to add null check debug information
-  int lock_object  (Register swap, Register obj, Register disp_hdr, Register tmp, Label& slow_case);
-
-  // unlocking
-  // hdr     : contents destroyed
-  // obj     : must point to the object to lock, contents preserved
-  // disp_hdr: must be x10 & must point to the displaced header location, contents destroyed
-  void unlock_object(Register swap, Register obj, Register lock, Label& slow_case);
-
-  void initialize_object(
-    Register obj,                      // result: pointer to object after successful allocation
-    Register klass,                    // object klass
-    Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
-    int      con_size_in_bytes,        // object size in bytes if   known at compile time
-    Register tmp1,                     // temp register
-    Register tmp2,                     // temp register
-    bool     is_tlab_allocated         // the object was allocated in a TLAB; relevant for the implementation of ZeroTLAB
-  );
-
-  // allocation of fixed-size objects
-  // (can also be used to allocate fixed-size arrays, by setting
-  // hdr_size correctly and storing the array length afterwards)
-  // obj        : will contain pointer to allocated object
-  // t1, t2     : temp registers - contents destroyed
-  // header_size: size of object header in words
-  // object_size: total size of object in words
-  // slow_case  : exit to slow case implementation if fast allocation fails
-  void allocate_object(Register obj, Register tmp1, Register tmp2, int header_size, int object_size, Register klass, Label& slow_case);
-
-  enum {
-    max_array_allocation_length = 0x00FFFFFF
-  };
-
-  // allocation of arrays
-  // obj        : will contain pointer to allocated object
-  // len        : array length in number of elements
-  // t          : temp register - contents destroyed
-  // header_size: size of object header in words
-  // f          : element scale factor
-  // slow_case  : exit to slow case implementation if fast allocation fails
-  void allocate_array(Register obj, Register len, Register tmp1, Register tmp2, int header_size, int f, Register klass, Label& slow_case);
-
-  int  rsp_offset() const { return _rsp_offset; }
-
-  void invalidate_registers(bool inv_r0, bool inv_r19, bool inv_r2, bool inv_r3, bool inv_r4, bool inv_r5) PRODUCT_RETURN;
-
-  // This platform only uses signal-based null checks. The Label is not needed.
-  void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); }
-
-  void load_parameter(int offset_in_words, Register reg);
-
-  void inline_cache_check(Register receiver, Register iCache, Label &L);
-
-  static const int c1_double_branch_mask = 1 << 3; // depend on c1_float_cond_branch
-  void c1_cmp_branch(int cmpFlag, Register op1, Register op2, Label& label, BasicType type, bool is_far);
-  void c1_float_cmp_branch(int cmpFlag, FloatRegister op1, FloatRegister op2, Label& label,
-                           bool is_far, bool is_unordered = false);
-
-#endif // CPU_RISCV_C1_MACROASSEMBLER_RISCV_HPP

src/hotspot/cpu/riscv/c1_globals_riscv.hpp

@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_RISCV_C1_GLOBALS_RISCV_HPP
-#define CPU_RISCV_C1_GLOBALS_RISCV_HPP
-
-#include "utilities/globalDefinitions.hpp"
-#include "utilities/macros.hpp"
-
-// Sets the default values for platform dependent flags used by the client compiler.
-// (see c1_globals.hpp)
-
-#ifndef COMPILER2
-define_pd_global(bool, BackgroundCompilation,        true );
-define_pd_global(bool, InlineIntrinsics,             true );
-define_pd_global(bool, PreferInterpreterNativeStubs, false);
-define_pd_global(bool, ProfileTraps,                 false);
-define_pd_global(bool, UseOnStackReplacement,        true );
-define_pd_global(bool, TieredCompilation,            false);
-define_pd_global(intx, CompileThreshold,             1500 );
-
-define_pd_global(intx, OnStackReplacePercentage,     933  );
-define_pd_global(intx, NewSizeThreadIncrease,        4*K  );
-define_pd_global(intx, InitialCodeCacheSize,         160*K);
-define_pd_global(intx, ReservedCodeCacheSize,        32*M );
-define_pd_global(intx, NonProfiledCodeHeapSize,      13*M );
-define_pd_global(intx, ProfiledCodeHeapSize,         14*M );
-define_pd_global(intx, NonNMethodCodeHeapSize,       5*M  );
-define_pd_global(bool, ProfileInterpreter,           false);
-define_pd_global(intx, CodeCacheExpansionSize,       32*K );
-define_pd_global(uintx, CodeCacheMinBlockLength,     1);
-define_pd_global(uintx, CodeCacheMinimumUseSpace,    400*K);
-define_pd_global(bool, NeverActAsServerClassMachine, true );
-define_pd_global(uint64_t, MaxRAM,                   1ULL*G);
-define_pd_global(bool, CICompileOSR,                 true );
-#endif // !COMPILER2
-define_pd_global(bool, UseTypeProfile,               false);
-
-define_pd_global(bool, OptimizeSinglePrecision,      true );
-define_pd_global(bool, CSEArrayLength,               false);
-define_pd_global(bool, TwoOperandLIRForm,            false);
-
-#endif // CPU_RISCV_C1_GLOBALS_RISCV_HPP